README.md
# F1C100S Linux dev board
A 58 × 48 mm, four-layer tscircuit board using a **vendored single-sided-assembly revision of astra/f1c100s 0.11.0**. The module is a reusable circuit layout, not a separately purchased plug-in PCB: its processor, support parts, and stored traces become part of this board.
The module’s seven bulk capacitors and three 10 µF reference filters now use 0805 footprints on the top side. The six carrier regulator reservoir capacitors also use 0805 footprints and remain on top. All sixteen have explicit manufacturer part numbers and voltage ratings. See [bulk capacitor selection](modules/f1c100s/docs/bulk-capacitors.md) for DC-bias data. This board uses single-sided component assembly.
The compact carrier uses 33.7% less area than the original 70 × 60 mm board. The four mounting holes are now on 50 × 40 mm centers.
## Included
- F1C100S processor with integrated 32 MiB RAM; imported 24 MHz clock, decoupling, reference circuits, reset RC, and bus pull-ups.
- W25Q128JVSIQ 16 MiB SPI NOR on SPI0 for SPL/U-Boot and a compact Linux/root filesystem.
- JST-PH 6-pin SPI1 breakout; independent of boot flash.
- JST-PH 4-pin I²C0 breakout; the module already supplies 4.7 kΩ pull-ups.
- USB-C USB 2.0 device port for FEL programming and 5 V power; separate TX/RX/GND UART debug pads.
- One SK9822-A clocked addressable RGB LED with a 5 V AHCT level shifter, reset button, removable flash-CS boot shunt.
- AP2112M SO-8 3.3 V and AP2112K SOT-25 1.8 V / 1.2 V LDOs: 5 V → 3.3 V, then 3.3 V → 1.8 V and 1.2 V.
- USBLC6 ESD protection and four 3.2 mm mounting holes, on 50 × 40 mm centers.
## Open and build
```sh
npm ci
npm run dev
npm run build
npm run typecheck
npm run verify
```
The main circuit is `index.circuit.tsx`. It imports the editable module from `modules/f1c100s/src`. Only the 25 truthy entries in the module’s `connections` create exit pads; the other 46 external breakouts are omitted. Internal support wiring remains connected. Each of the 15 dedicated decouplers has an explicit capacitor-to-processor-pin trace (for example, `C_D31.pin1 → U1.pin31`), and stored routing requires that physical branch before routing the shared rail. All 15 dedicated supply branches stay on the top layer without vias; the longest native-profile branch is 3.15 mm (previously 9.46 mm). Their ground pads have a GND via within 1.3 mm. The crystal is rotated to match processor clock-pin order. Regulator, flash and ESD capacitors face their target pins and connect through explicit pin-target traces. Bulk capacitors remain on their supply nets. `routing-boundary.ts` makes the module-center reservation routing-only: native routing sees it, then the synthetic keepouts are removed before copper filling and the normal full copper checks. Existing module copper is preserved, and actual trace/via/connectivity errors are not suppressed. Parent ground and USB nets have distinct names to avoid clashes with the imported module's internal net names in this pinned toolchain.
`dist/index/pcb.svg`, `dist/index/schematic.svg`, and `dist/index/circuit.json` are generated previews and the complete circuit model. `verification.json` records the most recent electrical assertions and emitted DRC errors. The circuit file is the editable source of truth.
## Validation status
The final `tsci build --site` and TypeScript check pass. All 32 module regression checks pass, covering empty/partial/full connections across five profiles, preserved copper, parent routing and rotated instances. `npm run verify` passes 103 electrical assertions, also passes 61 decoupling assertions and 30 carrier placement assertions, plus 64 bulk-capacitor assertions, checks the board dimensions, and reports **zero emitted DRC errors**. The model contains 109 PCB components (including 25 selected module exits and three bare UART pads), 238 PCB traces, and 201 vias. Connector, addressable LED, and board previews were visually inspected. Warnings about imported reference-designator conventions and React keys remain non-fatal. This is a PCB design prototype; no physical hardware or bootable image has been tested.
## Connector pinouts
USB-C J_USB is a TYPE-C-31-M-12 (JLCPCB C165948), oriented outward at the top board edge. It connects 5 V VBUS and the F1C100S native USB D+/D− pair. Both D+ contacts are joined, as are both D− contacts. CC1 and CC2 each have their own 5.1 kΩ pull-down (C23186); SBU pins are unconnected. The shell is grounded. This is a USB 2.0 device/sink port with no USB-PD negotiation, host mode, or USB-to-UART bridge.
The three bare UART debug holes have 2.54 mm pitch and are labeled TX, RX, GND from left to right when viewing the top side with USB at the top. TX is UART0/PE1, a board output; RX is UART0/PE0, a board input. Use a **3.3 V logic** adapter: board TX to adapter RX, board RX to adapter TX, and common ground. No adapter power connection is provided. These are solder/debug holes, not fitted BOM parts. USB alone provides FEL programming, not the hardware UART console.
All JST pin numbers refer to footprint pads, not cable colors. JST-PH is 2.00 mm pitch; these custom pinouts are not Qwiic/STEMMA QT.
| Pin | J_SPI — B6B-PH-K-S | J_I2C — B4B-PH-K-S |
|---|---|---|
| 1 | Ground | Ground |
| 2 | +3.3 V output | +3.3 V output |
| 3 | SPI1 clock / PE9 | I²C0 SDA / PE12 |
| 4 | SPI1 MOSI / PE8 | I²C0 SCL / PE11 |
| 5 | SPI1 MISO / PE10 | — |
| 6 | SPI1 CS / PE7 | — |
Mating housings: PHR-6 and PHR-4 with compatible JST PH crimp contacts. Power through USB-C using a data-capable cable for FEL. SPI and I²C use 3.3 V logic. Do not connect an external power output to the 3.3 V breakout pins.
## Boot and programming
Fit a 2.54 mm two-pin shunt on JP_BOOT for normal flash boot. Removing it disconnects only flash CS; R_FLASH_CS holds the flash deselected. With no other boot storage fitted, reset/power-up falls through to the SoC USB FEL ROM.
1. Power off, remove JP_BOOT, and connect a USB-C data cable.
2. Power up and check discovery with `sunxi-fel --list --verbose` (use a sunxi-tools build supporting F1C100S/suniv).
3. After the ROM is idle in FEL, refit JP_BOOT without resetting so the flash can be accessed. Use an insulated shunt and avoid adjacent pads.
4. Load a suitable F1C100S SPL/U-Boot into RAM over FEL and program the SPI NOR using that bootloader's supported flash workflow. The image must match 32 MiB RAM, this pin mux, and your flash partition layout.
5. Reset with JP_BOOT fitted. Console convention is 115200 8N1, configured on PE0/PE1 in both bootloader and kernel.
Blank flash can enter FEL with the shunt already fitted. No bootable image is bundled. `firmware/carrier.dtsi` supplies kernel integration pin assignments and LED nodes; it must be included in a complete board DTS and built with your chosen kernel/U-Boot tree.
## RGB programming
The SK9822-A (JLCPCB C5378730) includes its RGB drivers, PWM, and serial interface. PE2 sends data and PE3 sends clock through a 74AHCT2G125 (C554633) powered from 5 V. Two 470 Ω series resistors limit edge ringing; two 100 kΩ input pull-downs hold the bus low while the GPIOs are unconfigured. The LED and buffer each have a directly connected 100 nF bypass capacitor. LED cascade outputs are unconnected; PE4 is no longer broken out.
The [SK9822-A Rev.01 datasheet](https://www.normandled.com/upload/202005/SK9822-A%20LED%20Datasheet.pdf) specifies **GRB** byte order for this exact variant, a 32-zero start frame, a pixel header with five brightness bits, and a 32-one end frame. Its clocked interface permits slow GPIO writes under Linux without WS2812-style sub-microsecond pulse timing. The LED retains the last color between updates. Do not use an unmodified BGR APA102 driver for this part.
The demo limits global brightness to **2/31**. Using the 18 mA/channel nominal rating, full white is approximately 3.5 mA of LED current plus up to 1 mA of control current. This is a software limit, not a hardware current limit: maximum brightness can draw roughly 54 mA, and the power-on state is not guaranteed dark. Initialize the LED early during boot if needed.
Install libgpiod 2.x Python bindings in your Linux image, enable GPIO character devices, and use `gpioinfo` to identify the PIO chip with lines named PE2 and PE3. Keep these pins free of other device-tree consumers; the old `gpio-leds` node has been removed. For example:
```sh
python3 firmware/rgb-demo.py --chip /dev/gpiochip0 --demo
python3 firmware/rgb-demo.py --chip /dev/gpiochip0 --rgb 0 255 0 --seconds 10
python3 firmware/rgb-demo.py --rgb 255 0 0 --dry-run
```
The program initializes off, displays at low brightness, and switches off on exit. `rgb-demo.sh` invokes the demo for compatibility. Frame order, off framing, and brightness-limit checks pass locally; GPIO signaling still needs verification on physical hardware. The firmware is an integration example, not a supplied Linux image.
## Electrical and fabrication limits
- Four copper layers are required. The module routes on all four; there is no dedicated uninterrupted ground plane. Ground pours fill available space.
- Minimum module trace width 0.12 mm, clearance 0.10 mm, via copper 0.45 mm, drill 0.20 mm. Review the selected fabricator's actual stackup and rules.
- AP2112 current ratings do not define a 600 mA peripheral budget. The 3.3 V LDO supplies the CPU I/O, flash, both lower-voltage LDO inputs, and breakouts. At 300 mA total, its dissipation is about 0.51 W at 5 V input. Verify temperature and supply stability under the intended Linux workload; keep external loads modest (initial design budget: 50 mA combined, subject to measured headroom).
- Power-up sequencing, regulator transient response, oscillator startup, and USB signal integrity need prototype measurements. USB's 90 Ω differential impedance must be finalized against the chosen stackup; automatic clearance checks alone do not establish USB compliance.
- The software checks establish net connectivity and geometric rules, not that Linux has booted on physical hardware. Do not treat a preview as hardware validation.
## Design references
- [Requested astra/f1c100s module](https://tscircuit.com/astra/f1c100s#files), including its README and support-circuit audit.
- [Sipeed Lichee Nano reference schematic](https://dl.sipeed.com/LICHEE/Nano/HDK/lichee_nano_8.16%28Schematic%29.pdf).
- [Linux F1C100S pin-control driver](https://github.com/torvalds/linux/blob/master/drivers/pinctrl/sunxi/pinctrl-suniv-f1c100s.c).
- [AP2112 datasheet](https://www.diodes.com/datasheet/download/AP2112.pdf).
- [SK9822-A datasheet](https://www.normandled.com/upload/202005/SK9822-A%20LED%20Datasheet.pdf).
- [AHCT level-shifter datasheet](https://assets.nexperia.com/documents/data-sheet/74AHC_AHCT2G125.pdf).
- [USB-C connector drawing](https://datasheet.lcsc.com/lcsc/1903211732_Korean-Hroparts-Elec-TYPE-C-31-M-12_C165948.pdf).
- [USB-C device/sink design guidance](https://docs.espressif.com/projects/esp-iot-solution/en/latest/usb/usb_overview/usb_typec_hardware_guide.html).
- [USBLC6 datasheet](https://www.st.com/resource/en/datasheet/usblc6-2.pdf).
- [sunxi-tools](https://github.com/linux-sunxi/sunxi-tools).
## Published package and fabrication exports
Published as [seveibar/f1c1990s-dev-board](https://tscircuit.com/seveibar/f1c1990s-dev-board), version 1.8.0. The processor remains F1C100S; the registry slug follows the requested name.
The `fabrication/` directory contains the Gerbers, plated and non-plated drills, BOM, pick-and-place data, routing DSN, and export checks. Read `fabrication/README.md` for layer order and assembly limitations. These files come from the verified, fully routed 58 × 48 mm layout.
## Inventory and 3D models
See `inventory-check.md` for stock shortages and exact supplier selections. The 58 × 48 mm revision is 6.5% smaller than the previous 62 × 48 mm carrier. `assembly-models.json` restores CAD metadata dropped by module inflation: supplier models for major components, procedural models for passive packages and the boot header, and supplier package models for the SK9822-A and its buffer. `assembly-metadata.ts` applies this metadata without changing electrical routing or pads. The two AP2112K regulators share a SOT-25 package model; U_3V3 retains its SO-8 model. All 81 fitted parts have explicit JLCPCB numbers. The [AP2112 datasheet](https://www.diodes.com/datasheet/download/AP2112.pdf) specifies 184 °C/W junction-to-ambient for SOT-25: the 1.2 V regulator dissipates 0.21 W at 100 mA from 3.3 V (about 39 °C rise under that test condition). Its 600 mA rating is not a continuous thermal budget for this layout.
## Single-sided assembly
All 81 physical components mount on the top side, including the ten 0805 bulk/reference capacitors previously placed underneath. The board remains 58 × 48 mm with four copper layers and mounting holes on 50 × 40 mm centers. Through-hole headers are inserted from the top. Only the top solder-paste stencil is required. Inventory shortages listed above are unchanged.
The carrier routing phase targets 0.13 mm trace-to-pad, pad-to-pad, and via-to-pad spacing while the existing module retains its validated 0.10 mm rules. A small 0.8 × 1.1 mm routing reservation at (13.3, 2.65) protects a stored trace at the module’s east edge; like the central reservation, it is removed before pouring and normal copper DRC. No copper or DRC errors are removed.
