seveibar/f1c100s-dev-board

This code defines the hardware layout and schematic for a four-layer F1C100S-based module, including footprint placement, pin mappings, power regulation, decoupling capacitors, support components, and routing configurations, enabling automated PCB generation, routing, and verification.

Version
1.3.0
License
unset
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Files

README.md

# F1C100S Linux dev board

A 62 Γ— 48 mm, four-layer tscircuit board using a **selective-breakout revision astra/f1c100s 0.11.0**. The module is a reusable circuit layout, not a separately purchased plug-in PCB: its processor, support parts, and stored traces become part of this board.

The module’s seven bulk capacitors and three 10 Β΅F reference filters now use 0805 footprints on the underside. The six carrier regulator reservoir capacitors also use 0805 footprints and remain on top. All sixteen have explicit manufacturer part numbers and voltage ratings. See [bulk capacitor selection](modules/f1c100s/docs/bulk-capacitors.md) for DC-bias data. This board requires two-sided assembly.

The compact carrier uses 29.1% less area than the original 70 Γ— 60 mm board. The four mounting holes are now on 54 Γ— 40 mm centers.

## Included

- F1C100S processor with integrated 32 MiB RAM; imported 24 MHz clock, decoupling, reference circuits, reset RC, and bus pull-ups.
- W25Q128JVSIQ 16 MiB SPI NOR on SPI0 for SPL/U-Boot and a compact Linux/root filesystem.
- JST-PH 6-pin SPI1 breakout; independent of boot flash.
- JST-PH 4-pin IΒ²C0 breakout; the module already supplies 4.7 kΞ© pull-ups.
- JST-PH 6-pin USB FEL programming + UART console + 5 V power connector.
- One programmable RGB LED, three transistor drivers, reset button, removable flash-CS boot shunt.
- Three AP2112 SO-8 LDOs: 5 V β†’ 3.3 V, then 3.3 V β†’ 1.8 V and 1.2 V.
- USBLC6 ESD protection and four 3.2 mm mounting holes, on 54 Γ— 40 mm centers.

## Open and build

```sh
npm ci
npm run dev
npm run build
npm run typecheck
npm run verify
```

The main circuit is `index.circuit.tsx`. It imports the editable module from `modules/f1c100s/src`. Only the 26 truthy entries in the module’s `connections` create exit pads; the other 45 external breakouts are omitted. Internal support wiring remains connected. Each of the 15 dedicated decouplers has an explicit capacitor-to-processor-pin trace (for example, `C_D31.pin1 β†’ U1.pin31`), and stored routing requires that physical branch before routing the shared rail. All 15 dedicated supply branches stay on the top layer without vias; the longest native-profile branch is 3.15 mm (previously 9.46 mm). Their ground pads have a GND via within 1.3 mm. The crystal is rotated to match processor clock-pin order. Regulator, flash and ESD capacitors face their target pins and connect through explicit pin-target traces. Bulk capacitors remain on their supply nets. `routing-boundary.ts` makes the module-center reservation routing-only: native routing sees it, then the synthetic keepout is removed before copper filling and the normal full copper checks. Existing module copper is preserved, and actual trace/via/connectivity errors are not suppressed. Parent ground and USB nets have distinct names to avoid clashes with the imported module's internal net names in this pinned toolchain.

`dist/index/pcb.svg`, `dist/index/schematic.svg`, and `dist/index/circuit.json` are generated previews and the complete circuit model. `verification.json` records the most recent electrical assertions and emitted DRC errors. The circuit file is the editable source of truth.

## Validation status

The final `tsci build --site` and TypeScript check pass. All 32 module regression checks pass, covering empty/partial/full connections across five profiles, preserved copper, parent routing and rotated instances. `npm run verify` passes 74 electrical assertions, also passes 61 decoupling assertions and 24 carrier placement assertions, plus 64 bulk-capacitor assertions, checks the board dimensions, and reports **zero emitted DRC errors**. The model contains 110 PCB components (including 26 selected module test points), 230 PCB traces, and 200 vias. Connector, RGB-driver, and board previews were visually inspected. Warnings about imported reference-designator conventions and React keys remain non-fatal. This is a PCB design prototype; no physical hardware or bootable image has been tested.

## Connector pinouts

All pin numbers refer to the PCB footprint's numbered pads, **not cable colors or an assumed mating-side view**. J_PROG and J_SPI use the same housing; label the harnesses. JST-PH is 2.00 mm pitch. These are custom pinouts, not Qwiic/STEMMA QT connectors.

| Pin | J_PROG β€” B6B-PH-K-S | J_SPI β€” B6B-PH-K-S | J_I2C β€” B4B-PH-K-S |
|---|---|---|---|
| 1 | +5 V input | Ground | Ground |
| 2 | USB Dβˆ’ | +3.3 V output | +3.3 V output |
| 3 | USB D+ | SPI1 clock / PE9 | IΒ²C0 SDA / PE12 |
| 4 | Ground | SPI1 MOSI / PE8 | IΒ²C0 SCL / PE11 |
| 5 | UART0 TX / PE1, board output | SPI1 MISO / PE10 | β€” |
| 6 | UART0 RX / PE0, board input | SPI1 CS / PE7 | β€” |

Mating housings: PHR-6 and PHR-4 with compatible JST PH crimp contacts. UART, SPI, and IΒ²C are **3.3 V logic**. Connect board TX to adapter RX and board RX to adapter TX. J_PROG needs a custom harness: pins 1–4 connect to USB, pins 5–6 to a 3.3 V UART adapter sharing ground. A UART adapter alone does not provide USB FEL flashing.

Power through J_PROG pin 1 from a regulated 5 V source. Do not connect a second adapter power output to the 3.3 V breakout pins. Start bring-up with a current-limited supply. Use a short USB harness with D+/Dβˆ’ kept together; a loose long JST cable is not a controlled-impedance USB cable.

## Boot and programming

Fit a 2.54 mm two-pin shunt on JP_BOOT for normal flash boot. Removing it disconnects only flash CS; R_FLASH_CS holds the flash deselected. With no other boot storage fitted, reset/power-up falls through to the SoC USB FEL ROM.

1. Power off, remove JP_BOOT, and connect the USB programming harness.
2. Power up and check discovery with `sunxi-fel --list --verbose` (use a sunxi-tools build supporting F1C100S/suniv).
3. After the ROM is idle in FEL, refit JP_BOOT without resetting so the flash can be accessed. Use an insulated shunt and avoid adjacent pads.
4. Load a suitable F1C100S SPL/U-Boot into RAM over FEL and program the SPI NOR using that bootloader's supported flash workflow. The image must match 32 MiB RAM, this pin mux, and your flash partition layout.
5. Reset with JP_BOOT fitted. Console convention is 115200 8N1, configured on PE0/PE1 in both bootloader and kernel.

Blank flash can enter FEL with the shunt already fitted. No bootable image is bundled. `firmware/carrier.dtsi` supplies kernel integration pin assignments and LED nodes; it must be included in a complete board DTS and built with your chosen kernel/U-Boot tree.

## RGB programming

Red = PE2, green = PE3, blue = PE4. GPIO HIGH turns a channel on through its NPN transistor; external base pull-downs default all channels off. The WΓΌrth 150141M173100 common anode runs from 5 V; cathode pin 3 is red, pin 4 green, pin 2 blue. Series resistors set approximately 4 mA per channel, with brightness dependent on LED forward voltage.

After integrating the DTS fragment and enabling `CONFIG_LEDS_GPIO`, run `firmware/rgb-demo.sh` as root to cycle colors. Each channel is independently programmable; the example uses on/off control. Smooth intensity mixing requires software PWM or an external PWM driver; three independent hardware PWM channels are not provided on these selected pins.

## Electrical and fabrication limits

- Four copper layers are required. The module routes on all four; there is no dedicated uninterrupted ground plane. Ground pours fill available space.
- Minimum module trace width 0.12 mm, clearance 0.10 mm, via copper 0.45 mm, drill 0.20 mm. Review the selected fabricator's actual stackup and rules.
- AP2112 current ratings do not define a 600 mA peripheral budget. The 3.3 V LDO supplies the CPU I/O, flash, both lower-voltage LDO inputs, and breakouts. At 300 mA total, its dissipation is about 0.51 W at 5 V input. Verify temperature and supply stability under the intended Linux workload; keep external loads modest (initial design budget: 50 mA combined, subject to measured headroom).
- Power-up sequencing, regulator transient response, oscillator startup, and USB signal integrity need prototype measurements. USB's 90 Ξ© differential impedance must be finalized against the chosen stackup; automatic clearance checks alone do not establish USB compliance.
- The software checks establish net connectivity and geometric rules, not that Linux has booted on physical hardware. Do not treat a preview as hardware validation.

## Design references

- [Requested astra/f1c100s module](https://tscircuit.com/astra/f1c100s#files), including its README and support-circuit audit.
- [Sipeed Lichee Nano reference schematic](https://dl.sipeed.com/LICHEE/Nano/HDK/lichee_nano_8.16%28Schematic%29.pdf).
- [Linux F1C100S pin-control driver](https://github.com/torvalds/linux/blob/master/drivers/pinctrl/sunxi/pinctrl-suniv-f1c100s.c).
- [AP2112 datasheet](https://www.diodes.com/datasheet/download/AP2112.pdf).
- [RGB LED datasheet](https://www.we-online.com/components/products/datasheet/150141M173100.pdf).
- [USBLC6 datasheet](https://www.st.com/resource/en/datasheet/usblc6-2.pdf).
- [MMBT3904 datasheet](https://www.diodes.com/datasheet/download/MMBT3904.pdf).
- [sunxi-tools](https://github.com/linux-sunxi/sunxi-tools).