seveibar/f1c100s-dev-board

This code defines the hardware layout and schematic for a four-layer F1C100S-based module, including footprint placement, pin mappings, power regulation, decoupling capacitors, support components, and routing configurations, enabling automated PCB generation, routing, and verification.

Version
1.3.0
License
unset
Stars
0

verification.json

{
  "bulkCapacitorAssertions": 64,
  "carrierPlacementAssertions": 24,
  "dedicatedDecouplers": 15,
  "decouplingAssertions": 61,
  "selectedModuleBreakouts": 26,
  "electricalAssertions": 74,
  "pcbComponents": 110,
  "pcbTraces": 230,
  "pcbVias": 191,
  "errorsByType": {},
  "errors": []
}