seveibar/f1c100s-dev-board

This code defines the hardware layout and schematic for a four-layer F1C100S-based module, including footprint placement, pin mappings, power regulation, decoupling capacitors, support components, and routing configurations, enabling automated PCB generation, routing, and verification.

Version
1.3.0
License
unset
Stars
0

modules/f1c100s/src/generated/lcd_right_storage_left.metrics.json

PCBPCB preview for modules/f1c100s/src/generated/lcd_right_storage_left.metrics.json
SchematicSchematic preview for modules/f1c100s/src/generated/lcd_right_storage_left.metrics.json
{
  "profile": "lcd_right_storage_left",
  "inputHash": "e3ebea490ba48b8d4a124ccce4ce556a36db90bd39b6873847c265a2cbeb0bd6",
  "moduleSizeMm": 28,
  "rules": {
    "traceWidth": 0.12,
    "clearance": 0.1,
    "viaDiameter": 0.45,
    "viaDrill": 0.2,
    "layers": 4
  },
  "platedTestPoints": 71,
  "nonTopExitContacts": 69,
  "traces": 176,
  "wireSegments": 1177,
  "vias": 222,
  "capacitors": 32,
  "localDecouplers": 15,
  "routedLengthMm": 1492.259,
  "usbDmLengthMm": 8.251748,
  "usbDpLengthMm": 8.251805,
  "usbSkewMm": 0.000057,
  "drcErrors": 0,
  "optimization": {
    "before": {
      "platedTestPoints": 71,
      "nonTopExitContacts": 69,
      "traces": 176,
      "wireSegments": 3599,
      "vias": 245,
      "capacitors": 32,
      "localDecouplers": 15,
      "routedLengthMm": 1557.425,
      "usbDmLengthMm": 8.251748,
      "usbDpLengthMm": 8.251805,
      "usbSkewMm": 0.000057
    },
    "after": {
      "platedTestPoints": 71,
      "nonTopExitContacts": 69,
      "traces": 176,
      "wireSegments": 1177,
      "vias": 222,
      "capacitors": 32,
      "localDecouplers": 15,
      "routedLengthMm": 1492.259,
      "usbDmLengthMm": 8.251748,
      "usbDpLengthMm": 8.251805,
      "usbSkewMm": 0.000057
    }
  }
}