seveibar/f1c100s-dev-board

This code defines the hardware layout and schematic for a four-layer F1C100S-based module, including footprint placement, pin mappings, power regulation, decoupling capacitors, support components, and routing configurations, enabling automated PCB generation, routing, and verification.

Version
1.3.0
License
unset
Stars
0

modules/f1c100s/src/generated/lcd_right_storage_bottom.metrics.json

PCBPCB preview for modules/f1c100s/src/generated/lcd_right_storage_bottom.metrics.json
SchematicSchematic preview for modules/f1c100s/src/generated/lcd_right_storage_bottom.metrics.json
{
  "profile": "lcd_right_storage_bottom",
  "inputHash": "2d7fbdee681beb93bf2f441258a6ce9267d2abf4dae21560c855173b57b55966",
  "moduleSizeMm": 28,
  "rules": {
    "traceWidth": 0.12,
    "clearance": 0.1,
    "viaDiameter": 0.45,
    "viaDrill": 0.2,
    "layers": 4
  },
  "platedTestPoints": 71,
  "nonTopExitContacts": 69,
  "traces": 176,
  "wireSegments": 1157,
  "vias": 219,
  "capacitors": 32,
  "localDecouplers": 15,
  "routedLengthMm": 1442.256,
  "usbDmLengthMm": 8.251748,
  "usbDpLengthMm": 8.251805,
  "usbSkewMm": 0.000057,
  "drcErrors": 0,
  "optimization": {
    "before": {
      "platedTestPoints": 71,
      "nonTopExitContacts": 69,
      "traces": 176,
      "wireSegments": 3511,
      "vias": 245,
      "capacitors": 32,
      "localDecouplers": 15,
      "routedLengthMm": 1501.77,
      "usbDmLengthMm": 8.251748,
      "usbDpLengthMm": 8.251805,
      "usbSkewMm": 0.000057
    },
    "after": {
      "platedTestPoints": 71,
      "nonTopExitContacts": 69,
      "traces": 176,
      "wireSegments": 1157,
      "vias": 219,
      "capacitors": 32,
      "localDecouplers": 15,
      "routedLengthMm": 1442.256,
      "usbDmLengthMm": 8.251748,
      "usbDpLengthMm": 8.251805,
      "usbSkewMm": 0.000057
    }
  }
}