0hmX/simplified-am62l-computer

This code defines components and scripts for physically representing and routing high-speed DDR memory signals, power lines, and ground planes on an 8-layer PCB with detailed pin assignments, copper pours, and precise via and trace layouts based on TI EVM reference data.

Version
1.0.16
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repros/am62l-lpddr4-breakout-repro/README.md

# AM62L32 ↔ LPDDR4 automatic-breakout reproduction

[View the published tscircuit package](https://tscircuit.com/0hmX/am62l-lpddr4-breakout-repro).

This minimal tscircuit project connects exactly 33 direct DDR signals between a
TI AM62L32 (`fccsp_373_anb`) and a Micron MT53E1G16D1ZW LPDDR4 device. Each BGA
is the sole component inside its own sibling `<breakout>`. The traces, buses,
and three differential-pair declarations live at board scope so every signal
crosses both breakout boundaries.

Core must automatically create both sets of breakout points, route both BGA
fanouts, synchronize their exits into the parent connections, and then run the
normal board autorouter through the middle. The source contains no manual vias,
breakout points, PCB trace primitives, route coordinates, custom autorouter, or
phase-index forcing.

## Important limitation

This is a 33-signal routing reproduction only. It intentionally omits all DDR
power, ground, decoupling, reference-voltage, termination, stackup, impedance,
and timing-signoff requirements. It is not a complete DDR design and is not
manufacturable.

## Pinned baseline

- `tscircuit`: `0.0.2332`
- `@tscircuit/core`: `0.0.1685`
- Core git commit / npm `gitHead`: `5ef2b914d1065733b06b3e1171eac3f66d0a319e`
- `@tsci/tscircuit.ti`: `1.0.100`
- `@tsci/0hmX.mt53e1g16d1zw-footprint`: `1.0.2`

The exact Core dependency is both direct and overridden in `package.json`; no
machine-specific `file:` dependency is used.

## Commands

```sh
bun install
bun run typecheck
bun run build
bun run snapshot
bun run build:pcb
bun run verify
```

`build` (and its `build:pcb` alias) enables PCB SVG/PNG generation plus
autorouter phase diagnostics and records wall-clock time in
`dist/routing-timing.json`. `verify` checks the
structural invariants and writes `dist/verification-report.json` while reporting
all routing and clearance errors without hiding an automatic-routing failure.

See `RESULTS.md` for the attempted configurations and observed outcome.