0hmX/simplified-am62l-computer
This code defines components and scripts for physically representing and routing high-speed DDR memory signals, power lines, and ground planes on an 8-layer PCB with detailed pin assignments, copper pours, and precise via and trace layouts based on TI EVM reference data.
- Version
- 1.0.16
- License
- unset
- Stars
- 0
index.circuit.tsx
PCB
Schematic
import { TPS6521401VAFR } from "@tsci/0hmX.tps6521401vafr-pmic"
import { AM62L32 } from "@tsci/tscircuit.ti"
import { RegistryMt53e1g16 } from "./components/registry-memory"
import { Fragment } from "react"
import { createAm62lClassifiedAutorouter } from "./routing/am62l-classified-autorouter"
import { createFixedTargetBgaFanoutAutorouter } from "./routing/fixed-target-bga-fanout-autorouter"
import { TI_AM62L_EVM_MEMORY_OFFSET } from "./routing/ti-am62l-evm-ddr-routes"
import { GRM155R71C104KA88D } from "./imports/GRM155R71C104KA88D"
import { CL05A105KP5NNNC } from "./imports/CL05A105KP5NNNC"
import { CL03A105KQ3CSNC } from "./imports/CL03A105KQ3CSNC"
import { TCC0201X7R104K160ZT } from "./imports/TCC0201X7R104K160ZT"
import { CL10A106KP8NNNC } from "./imports/CL10A106KP8NNNC"
import { CL10A226MP8NUNE } from "./imports/CL10A226MP8NUNE"
import { GRM155R61A225KE95D } from "./imports/GRM155R61A225KE95D"
import { CL05C100JB5NNNC } from "./imports/CL05C100JB5NNNC"
import { A_0402WGF5101TCE } from "./imports/A_0402WGF5101TCE"
import { A_0402WGF1001TCE } from "./imports/A_0402WGF1001TCE"
import { A_0402WGF1002TCE } from "./imports/A_0402WGF1002TCE"
import { A_0402WGF1003TCE } from "./imports/A_0402WGF1003TCE"
import { A_0402WGF2400TCE } from "./imports/A_0402WGF2400TCE"
import { A_0402WGF2201TCE } from "./imports/A_0402WGF2201TCE"
import { A_0402WGF4702TCE } from "./imports/A_0402WGF4702TCE"
import { A_0402WGF4701TCE } from "./imports/A_0402WGF4701TCE"
import { A_0402WGF0000TCE } from "./imports/A_0402WGF0000TCE"
import { A_0402WGF1000TCE } from "./imports/A_0402WGF1000TCE"
import { A_0402WGF4533TCE } from "./imports/A_0402WGF4533TCE"
import { A_0402WGF6651TCE } from "./imports/A_0402WGF6651TCE"
import { A_0402WGF2491TCE } from "./imports/A_0402WGF2491TCE"
import { A_0402WGF9093TCE } from "./imports/A_0402WGF9093TCE"
import { C1005X5R1A335KTJ00E } from "./imports/C1005X5R1A335KTJ00E"
import { A_0402B472K500NT } from "./imports/A_0402B472K500NT"
import { CL05C220JB5NNNC } from "./imports/CL05C220JB5NNNC"
import { CL05A475MP5NRNC } from "./imports/CL05A475MP5NRNC"
import { CL10B221KB8NNNC } from "./imports/CL10B221KB8NNNC"
import { SMF5_0A } from "./imports/SMF5_0A"
import { LTST_C190KRKT } from "./imports/LTST_C190KRKT"
import { SN74LVC1G04DBVR } from "./imports/SN74LVC1G04DBVR"
import { TLV75533PDBVR } from "./imports/TLV75533PDBVR"
import { TUSB320LAIRWBR } from "./imports/TUSB320LAIRWBR"
import { TFM201208BLE_R47MTCF } from "./imports/TFM201208BLE_R47MTCF"
import {
DFE201612PD_1R0M_P2,
DM3AT_SF_PEJM5,
LTST_C190KGKT,
S4B_PH_SM4_K_TB_LF__SN_,
SKRPACE010,
SN74AXC1T45DBVR,
SN74LVC1G08DBVR,
TPD2E2U06DCKR,
TPD4E02B04DQAR,
TPS22918DBVR,
TPS259470LRPWR,
TPS62A02DRLR,
USB4125_GF_A_0190,
XRCGB25M000F3A00R0,
} from "./imports/index"
type PinAttribute = { requiresPower?: boolean; requiresGround?: boolean; providesPower?: boolean }
/** Every physical pin is annotated, including deliberately unused pins. */
const pinMetadata = (
count: number,
connected: number[],
attributes: Record<number, PinAttribute> = {},
) => ({
noConnect: Array.from({ length: count }, (_, index) => index + 1)
.filter((pin) => !connected.includes(pin))
.map((pin) => `pin${pin}`),
pinAttributes: Object.fromEntries(
Array.from({ length: count }, (_, index) => [
`pin${index + 1}`,
attributes[index + 1] ?? {},
]),
),
}) as any
const socVssPins = [1, 2, 4, 10, 13, 16, 19, 22, 23, 24, 28, 40, 43, 46, 53, 56, 60, 77, 78, 79, 80, 81, 85, 86, 95, 96, 97, 106, 107, 108, 111, 114, 115, 116, 120, 126, 130, 132, 151, 152, 156, 166, 168, 170, 172, 174, 180, 187, 201, 203, 204, 205, 207, 218, 222, 226, 228, 231, 232, 237, 242, 243, 250, 258, 259, 261, 264, 265, 266, 268, 269, 274, 278, 279, 288, 289, 291, 293, 294, 295, 296, 299, 311, 312, 317, 325, 328, 334, 348, 350, 351, 352, 361, 364, 369, 372, 373]
const socFunctionalGroundPins = [112, 113, 129, 208, 245, 262, 263, 280, 281, 282, 283, 371]
const socGroundPins = [...socVssPins, ...socFunctionalGroundPins]
const socCore075Pins = [142, 143, 144, 145, 153, 155, 171, 186, 188, 206, 219, 220, 221, 229, 230]
const socRtc075Pins = [248]
const socDdr11Pins = [167, 184, 185, 202, 217]
const socFixed18Pins = [109, 128, 131, 146, 154, 169, 173, 190, 223, 233, 246, 249]
const socFixed33Pins = [127]
const socCapVddsPins = [110, 141, 157, 189, 260]
const socAttributes = Object.fromEntries([
...socGroundPins.map((pin) => [pin, { requiresGround: true }]),
...[...socCore075Pins, ...socRtc075Pins, ...socDdr11Pins, ...socFixed18Pins, ...socFixed33Pins, 244, 267]
.map((pin) => [pin, { requiresPower: true }]),
[247, { providesPower: true }],
...socCapVddsPins.map((pin) => [pin, { providesPower: true }]),
])
const socConnected = Array.from(new Set([
// MMC1 / microSD
29, 64, 244, 247, 267, 300, 301, 302, 315, 316, 329,
// UART0, reset, oscillator, PMIC control
51, 54, 55, 68, 87, 101, 102, 118, 119, 310, 324, 326, 345, 346, 347, 349, 367, 368,
// LPDDR4 x16 interface plus the controller calibration resistor pin.
76, 91, 92, 93, 94, 103, 104, 105, 121, 122, 123, 124, 125, 139, 140,
149, 150, 162, 164, 165, 182, 215, 216, 236, 238, 255, 256, 257, 272,
273, 275, 276, 284, 285,
...socGroundPins, ...socCore075Pins, ...socRtc075Pins, ...socDdr11Pins,
...socFixed18Pins, ...socFixed33Pins, ...socCapVddsPins,
]))
const ddrSignals: Array<[string, string]> = [
...Array.from({ length: 16 }, (_, bit) => [`DDR0_DQ${bit}`, `DQ${bit}`] as [string, string]),
["DDR0_DM0", "DMI0"], ["DDR0_DM1", "DMI1"],
["DDR0_DQS0", "DQS0_t"], ["DDR0_DQS0_n", "DQS0_c"],
["DDR0_DQS1", "DQS1_t"], ["DDR0_DQS1_n", "DQS1_c"],
["DDR0_A0", "CA0"], ["DDR0_A1", "CA1"], ["DDR0_A2", "CA2"],
["DDR0_A3", "CA3"], ["DDR0_A4", "CA4"], ["DDR0_A5", "CA5"],
["DDR0_CS0_n", "CS"], ["DDR0_CKE0", "CKE"],
["DDR0_CK0", "CK_t"], ["DDR0_CK0_n", "CK_c"], ["DDR0_RESET0_n", "RESET_n"],
]
const logicalTraces: Array<[string, string]> = [
// USB-C power-only input. A5/B5 are the independent CC pins; no USB data exists.
["U12.A9", "net.VBUS_RAW"], ["U12.B9", "net.VBUS_RAW"],
["U12.A12", "net.GND"], ["U12.B12", "net.GND"],
["U12.pin7", "net.GND"], ["U12.pin8", "net.GND"], ["U12.pin9", "net.GND"], ["U12.pin10", "net.GND"],
["U12.A5", "net.USB_CC1"], ["U12.B5", "net.USB_CC2"],
["U4.IN", "net.VBUS_RAW"], ["U4.OUT", "net.PROTECTED_5V"], ["U4.GND", "net.GND"],
["U4.EN_UVLO", "net.EFUSE_EN"], ["U4.OVLO", "net.EFUSE_OVLO"],
["U4.DVDT", "net.EFUSE_DVDT"], ["U4.ILM", "net.EFUSE_ILM"],
["D2.pin1", "net.VBUS_RAW"], ["D2.pin2", "net.GND"],
// TUSB320LAI UFP/sink-only CC detection. PORT=0 selects UFP, ADDR open selects GPIO mode,
// and EN_N=0 enables the internal Rd terminations. OUT1 is low only for 1.5A/3A Rp.
["U21.CC1", "net.USB_CC1"], ["U21.CC2", "net.USB_CC2"],
["U21.PORT", "net.GND"], ["U21.VBUS_DET", "net.TUSB_VBUS_DET"],
["U21.OUT1", "net.TUSB_OUT1"], ["U21.OUT2", "net.TUSB_OUT2"],
["U21.GND", "net.GND"], ["U21.EN_N", "net.GND"], ["U21.VDD", "net.VBUS_RAW"],
// Raw-VBUS-powered 3V3 rail keeps TUSB GPIO pull-ups and enable logic alive before U4.
["U22.IN", "net.VBUS_RAW"], ["U22.EN", "net.VBUS_RAW"], ["U22.GND", "net.GND"],
["U22.OUT", "net.AON_3V3"],
// OUT1 high -> inverter low -> eFuse off. Only an advertised 1.5A/3A source pulls OUT1 low.
["U23.A", "net.TUSB_OUT1"], ["U23.Y", "net.EFUSE_EN"],
["U23.VCC", "net.AON_3V3"], ["U23.GND", "net.GND"],
// Default-current attached state is OUT1=H, OUT2=L. Decode it for the red warning LED.
["U24.A", "net.TUSB_OUT2"], ["U24.Y", "net.TUSB_OUT2_N"],
["U24.VCC", "net.AON_3V3"], ["U24.GND", "net.GND"],
["U25.A", "net.TUSB_OUT1"], ["U25.B", "net.TUSB_OUT2_N"],
["U25.Y", "net.WEAK_USB_LED_A"], ["U25.VCC", "net.AON_3V3"], ["U25.GND", "net.GND"],
["D3.anode", "net.WEAK_USB_LED_A"], ["D3.cathode", "net.WEAK_USB_LED_K"],
["TP_CC1.pin1", "net.USB_CC1"], ["TP_CC2.pin1", "net.USB_CC2"],
["TP_TUSB_OUT1.pin1", "net.TUSB_OUT1"], ["TP_EFUSE_EN.pin1", "net.EFUSE_EN"],
["TP_PROTECTED_5V.pin1", "net.PROTECTED_5V"],
// PMIC and external 3V3 supply.
["U3.VSYS", "net.PROTECTED_5V"], ["U3.PVIN_B1", "net.PROTECTED_5V"],
["U3.PVIN_B2", "net.PROTECTED_5V"], ["U3.PVIN_B3", "net.PROTECTED_5V"],
["U3.AGND", "net.GND"], ["U3.pin10", "net.GND"], ["U3.pin22", "net.GND"],
["U3.VLDO1", "net.VDDA_1V8"], ["U3.VLDO2", "net.VDD_RTC_0V75"],
["U3.FB_B1", "net.VDD_CORE_0V75"], ["U3.FB_B2", "net.VDD_1V8"],
["U3.FB_B3", "net.VDD_DDR_1V1"], ["U3.VDD1P8", "net.PMIC_VDD1P8"],
["U3.EN", "net.PROTECTED_5V"],
["U3.LX_B1", "net.PMIC_BUCK1_SW"], ["U3.LX_B2", "net.PMIC_BUCK2_SW"], ["U3.LX_B3", "net.PMIC_BUCK3_SW"],
["U3.SDA", "net.PMIC_I2C_SDA"], ["U3.SCL", "net.PMIC_I2C_SCL"],
["U3.nRSTOUT", "net.PMIC_nRSTOUT"], ["U3.GPO", "net.RTC_PORz"], ["U3.nINT", "net.PMIC_nINT"],
["U3.GPIO", "net.EXT_3V3_EN"],
["U5.VIN", "net.PROTECTED_5V"], ["U5.EN", "net.EXT_3V3_EN"], ["U5.GND", "net.GND"],
["U5.SW", "net.EXT_3V3_SW"], ["L1.pin1", "net.EXT_3V3_SW"], ["L1.pin2", "net.VDD_3V3"],
["U5.FB", "net.EXT_3V3_FB"], ["U5.PG", "net.EXT_3V3_PG"],
// Reset/clock/control.
["U11.A", "net.PMIC_nRSTOUT"], ["U11.B", "net.EXT_3V3_PG"], ["U11.Y", "net.SOC_PORz"],
["U11.VCC", "net.VDD_1V8"], ["U11.GND", "net.GND"], ["U1.PORz", "net.SOC_PORz"],
["U1.RTC_PORz", "net.RTC_PORz"], ["U1.RESETz", "net.RESETz"], ["U1.pin55", "net.RESETSTATz"],
["U1.pin51", "net.PMIC_nINT"],
["SW1.pin1", "net.RESETz"], ["SW1.pin2", "net.GND"], ["SW1.pin3", "net.RESETz"], ["SW1.pin4", "net.GND"],
["Y1.pin1", "net.OSC_25M_XI"], ["Y1.pin3", "net.OSC_25M_XO"], ["Y1.pin2", "net.GND"], ["Y1.pin4", "net.GND"],
["U1.WKUP_OSC0_XI", "net.OSC_25M_XI"], ["U1.WKUP_OSC0_XO", "net.OSC_25M_XO"],
["U1.WKUP_I2C0_SDA", "net.PMIC_I2C_SDA"], ["U1.WKUP_I2C0_SCL", "net.PMIC_I2C_SCL"],
["U1.PMIC_LPM_EN0", "net.PMIC_LPM_EN"], ["U3.MODE_STBY", "net.PMIC_LPM_EN"],
["U1.pin102", "net.BOOTMODE15"], ["U1.pin101", "net.BOOTMODE14"],
["U1.pin118", "net.BOOTMODE13"], ["U1.pin119", "net.BOOTMODE12"],
["U1.pin346", "net.EXT_WAKEUP0_UNUSED"], ["U1.pin347", "net.EXT_WAKEUP1_UNUSED"],
// microSD, supply switch, and two four-channel ESD arrays.
["U6.VIN", "net.VDD_3V3"], ["U6.VOUT", "net.SD_3V3"], ["U6.ON", "net.SD_PWR_EN"], ["U6.GND", "net.GND"],
["U6.CT", "net.SD_LOADSW_CT"],
["U15.VDD", "net.SD_3V3"], ["U15.VSS", "net.GND"], ["U15.CLK", "net.SD_CLK"], ["U15.CMD", "net.SD_CMD"],
["U15.DAT0", "net.SD_DAT0"], ["U15.DAT1", "net.SD_DAT1"], ["U15.DAT2", "net.SD_DAT2"], ["U15.pin2", "net.SD_DAT3"],
["U15.SW_A", "net.SD_CARD_DETECT"], ["U15.SW_B", "net.GND"],
["U1.MMC1_CLK", "net.SD_CLK_SOC"], ["U1.MMC1_CMD", "net.SD_CMD"], ["U1.MMC1_DAT0", "net.SD_DAT0"],
["U1.MMC1_DAT1", "net.SD_DAT1"], ["U1.MMC1_DAT2", "net.SD_DAT2"], ["U1.MMC1_DAT3", "net.SD_DAT3"],
["U1.MMC1_SDCD", "net.SD_CD_SOC"], ["U1.pin64", "net.SD_PWR_GPIO"],
["U7.IO1", "net.SD_CLK"], ["U7.IO2", "net.SD_CMD"], ["U7.IO3", "net.SD_DAT0"], ["U7.IO4", "net.SD_DAT1"],
["U7.GND1", "net.GND"], ["U7.GND2", "net.GND"],
["U8.IO1", "net.SD_DAT2"], ["U8.IO2", "net.SD_DAT3"], ["U8.IO3", "net.SD_CARD_DETECT"],
["U8.GND1", "net.GND"], ["U8.GND2", "net.GND"],
// UART0: fixed-direction translators, 3V3-safe connector, ESD protection.
["U9.VCCA", "net.VDD_1V8"], ["U9.VCCB", "net.VDD_3V3"], ["U9.GND", "net.GND"], ["U9.DIR", "net.VDD_1V8"],
["U9.A", "net.UART0_TX_1V8"], ["U9.B", "net.UART_TX_3V3"], ["U1.UART0_TXD", "net.UART0_TX_1V8"],
["U10.VCCA", "net.VDD_1V8"], ["U10.VCCB", "net.VDD_3V3"], ["U10.GND", "net.GND"], ["U10.DIR", "net.GND"],
["U10.A", "net.UART0_RX_1V8"], ["U10.B", "net.UART_RX_3V3"], ["U1.UART0_RXD", "net.UART0_RX_1V8"],
["U16.IO1", "net.UART_TX_3V3"], ["U16.IO2", "net.UART_RX_3V3"], ["U16.GND", "net.GND"],
["U17.pin1", "net.UART_TX_3V3"], ["U17.pin2", "net.UART_RX_3V3"], ["U17.pin3", "net.GND"], ["U17.pin4", "net.VDD_3V3"],
["D1.anode", "net.VDD_3V3"], ["D1.cathode", "net.POWER_LED_K"],
// LPDDR4 reference/calibration pins are shunted locally, not routed together.
["U1.DDR0_CAL0", "net.DDR0_CAL0"], ["U2.ZQ", "net.LPDDR4_ZQ"],
["U2.ODT_CA", "net.LPDDR4_ODT_CA"],
// SD power defaults on for ROM boot and is released only after RESETSTATz.
["U20.A", "net.SD_PWR_GPIO"], ["U20.B", "net.RESETSTATz"],
["U20.Y", "net.SD_PWR_EN"], ["U20.VCC", "net.VDD_1V8"], ["U20.GND", "net.GND"],
["TP_BOOT15.pin1", "net.BOOTMODE15"], ["TP_BOOT14.pin1", "net.BOOTMODE14"],
["TP_BOOT13.pin1", "net.BOOTMODE13"], ["TP_BOOT12.pin1", "net.BOOTMODE12"],
]
const socGroundTraces = socGroundPins.map((pin) => [`U1.pin${pin}`, "net.GND"] as [string, string])
const socRailTraces: Array<[string, string]> = [
...socCore075Pins.filter((pin) => pin !== 229).map((pin) => [`U1.pin${pin}`, "net.VDD_CORE_0V75"] as [string, string]),
...socRtc075Pins.map((pin) => [`U1.pin${pin}`, "net.VDD_RTC_0V75"] as [string, string]),
...socDdr11Pins.map((pin) => [`U1.pin${pin}`, "net.VDD_DDR_1V1"] as [string, string]),
...socFixed18Pins.filter((pin) => ![154, 169].includes(pin)).map((pin) => [`U1.pin${pin}`, "net.VDD_1V8"] as [string, string]),
...[154, 169].map((pin) => [`U1.pin${pin}`, "net.VDDA_1V8"] as [string, string]),
...socFixed33Pins.map((pin) => [`U1.pin${pin}`, "net.VDD_3V3"] as [string, string]),
["U1.pin267", "net.SD_3V3"], ["U1.pin247", "net.SD_IO"], ["U1.pin244", "net.SD_IO"],
["U1.pin110", "net.CAP_VDDS_GENERAL1"], ["U1.pin141", "net.CAP_VDDS_MMC0"],
["U1.pin157", "net.CAP_VDDS_GPMC"], ["U1.pin189", "net.CAP_VDDS_MMC2"],
["U1.pin260", "net.CAP_VDDS_MMC1"],
]
type CapacitorSpec = { name: string; value: string; jlc: string; net: string; x: number; y: number; rotation?: number; side?: "top" | "bottom" }
type ResistorSpec = { name: string; value: string; jlc: string; from: string; to: string; x: number; y: number; rotation?: number; side?: "top" | "bottom" }
const decouplingCapacitors: CapacitorSpec[] = [
// TEMP: disable capacitors beneath U1 until the breakout solver models component copper.
/*
// AM62L backside decoupling follows the projected supply-ball clusters.
// These are deliberately staggered to preserve signal escape channels; this
// is not a cosmetic grid. Bulk capacitors remain outside the package body.
{ name: "C1", value: "100nF", jlc: "C18164586", net: "VDD_CORE_0V75", x: 3.45, y: -1.2, side: "bottom" },
{ name: "C2", value: "100nF", jlc: "C18164586", net: "VDD_CORE_0V75", x: 1.25, y: -0.75, side: "bottom" },
{ name: "C3", value: "100nF", jlc: "C18164586", net: "VDD_CORE_0V75", x: 2.75, y: 0.25, side: "bottom" },
{ name: "C4", value: "100nF", jlc: "C18164586", net: "VDD_CORE_0V75", x: 1.05, y: 0.35, side: "bottom" },
{ name: "C5", value: "100nF", jlc: "C18164586", net: "VDD_CORE_0V75", x: 3.05, y: 1.45, side: "bottom" },
{ name: "C6", value: "100nF", jlc: "C18164586", net: "VDD_CORE_0V75", x: 1.35, y: 1.65, side: "bottom" },
{ name: "C7", value: "100nF", jlc: "C18164586", net: "VDD_CORE_0V75", x: 2.05, y: 2.85, side: "bottom" },
{ name: "C17", value: "100nF", jlc: "C18164586", net: "VDD_CORE_0V75", x: 0.05, y: 3.15, side: "bottom" },
{ name: "C18", value: "100nF", jlc: "C18164586", net: "VDD_CORE_0V75", x: 3.7, y: 2.55, side: "bottom" },
// Fixed 1.8V and 3.3V I/O clusters around the SoC perimeter.
{ name: "C8", value: "100nF", jlc: "C18164586", net: "VDD_1V8", x: 3.2, y: -2.7, side: "bottom" },
{ name: "C9", value: "100nF", jlc: "C18164586", net: "VDD_1V8", x: -0.1, y: -2.05, side: "bottom" },
{ name: "C10", value: "100nF", jlc: "C18164586", net: "VDD_1V8", x: -1.45, y: 0.45, side: "bottom" },
{ name: "C11", value: "100nF", jlc: "C18164586", net: "VDD_1V8", x: -1.55, y: 2.55, side: "bottom" },
{ name: "C13", value: "100nF", jlc: "C18164586", net: "VDD_3V3", x: 5.35, y: -1.25, side: "bottom" },
{ name: "C14", value: "100nF", jlc: "C18164586", net: "VDD_3V3", x: -2.75, y: -3.35, side: "bottom" },
{ name: "C15", value: "100nF", jlc: "C18164586", net: "VDD_3V3", x: -2.75, y: 4.05, side: "bottom" },
{ name: "C16", value: "100nF", jlc: "C18164586", net: "VDD_3V3", x: 6.25, y: -3.25, side: "bottom" },
{ name: "C20", value: "100nF", jlc: "C18164586", net: "VDD_3V3", x: 6.3, y: 4.2, side: "bottom" },
// One 100nF capacitor is dedicated to the SoC analog 1.8V pair, and one
// DDR capacitor is reserved for the SoC VDDS_DDR cluster instead of putting
// every capacitor beneath the memory package.
{ name: "C19", value: "100nF", jlc: "C18164586", net: "VDDA_1V8", x: 4.2, y: 0.8, side: "bottom" },
{ name: "C22", value: "100nF", jlc: "C18164586", net: "VDD_DDR_1V1", x: 5.15, y: 1.8, side: "bottom" },
*/
// TEMP: disable capacitors beneath U2 until the breakout solver models component copper.
/*
// LPDDR4 backside decoupling is split across the left/right VDD1 groups and
// the lower/middle/upper VDD2/VDDQ ball clusters.
{ name: "C21", value: "100nF", jlc: "C18164586", net: "VDD_1V8", x: 18.7, y: -2.8, side: "bottom" },
{ name: "C25", value: "100nF", jlc: "C18164586", net: "VDD_1V8", x: 25.7, y: -2.8, side: "bottom" },
{ name: "C29", value: "100nF", jlc: "C18164586", net: "VDD_1V8", x: 18.7, y: 4.7, side: "bottom" },
{ name: "C12", value: "100nF", jlc: "C18164586", net: "VDD_1V8", x: 25.7, y: 4.7, side: "bottom" },
{ name: "C23", value: "100nF", jlc: "C18164586", net: "VDD_DDR_1V1", x: 21.25, y: -2.55, side: "bottom" },
{ name: "C24", value: "100nF", jlc: "C18164586", net: "VDD_DDR_1V1", x: 27.9, y: -2.5, side: "bottom" },
{ name: "C26", value: "100nF", jlc: "C18164586", net: "VDD_DDR_1V1", x: 19.65, y: 0.3, rotation: 90, side: "bottom" },
{ name: "C27", value: "100nF", jlc: "C18164586", net: "VDD_DDR_1V1", x: 24.8, y: 0.2, rotation: 90, side: "bottom" },
{ name: "C28", value: "100nF", jlc: "C18164586", net: "VDD_DDR_1V1", x: 27.8, y: 0.5, rotation: 90, side: "bottom" },
{ name: "C30", value: "100nF", jlc: "C18164586", net: "VDD_DDR_1V1", x: 20.2, y: 4.3, side: "bottom" },
{ name: "C31", value: "100nF", jlc: "C18164586", net: "VDD_DDR_1V1", x: 23.7, y: 4.3, side: "bottom" },
{ name: "C32", value: "100nF", jlc: "C18164586", net: "VDD_DDR_1V1", x: 27.9, y: 4.3, side: "bottom" },
*/
// Input/output bulk and local peripheral bypass capacitors.
// Keep total receptacle-side VBUS capacitance within the 1uF-to-10uF UFP range.
{ name: "C33", value: "4.7uF", jlc: "C23733", net: "VBUS_RAW", x: -34.5, y: 2.5 },
{ name: "C34", value: "22uF", jlc: "C86295", net: "PROTECTED_5V", x: -7, y: 13.2 },
{ name: "C35", value: "10uF", jlc: "C19702", net: "PROTECTED_5V", x: -27, y: 2 },
{ name: "C36", value: "22uF", jlc: "C86295", net: "VDD_CORE_0V75", x: -6, y: -11.2 },
{ name: "C37", value: "22uF", jlc: "C86295", net: "VDD_1V8", x: -2, y: -11.2 },
{ name: "C38", value: "22uF", jlc: "C86295", net: "VDD_DDR_1V1", x: 2, y: -11.2 },
{ name: "C39", value: "2.2uF", jlc: "C77002", net: "PMIC_VDD1P8", x: -11, y: 12 },
{ name: "C40", value: "10uF", jlc: "C19702", net: "VDD_3V3", x: -10, y: -10 },
{ name: "C41", value: "22uF", jlc: "C86295", net: "VDD_3V3", x: -14, y: -10 },
{ name: "C42", value: "1uF", jlc: "C14445", net: "SD_3V3", x: -2, y: 24 },
{ name: "C43", value: "10uF", jlc: "C19702", net: "SD_3V3", x: 2.5, y: 27 },
{ name: "C44", value: "100nF", jlc: "C71629", net: "VDD_1V8", x: 19, y: -17 },
{ name: "C45", value: "100nF", jlc: "C71629", net: "VDD_3V3", x: 25, y: -16.5 },
{ name: "C46", value: "100nF", jlc: "C71629", net: "VDD_1V8", x: 24, y: -23 },
{ name: "C47", value: "100nF", jlc: "C71629", net: "VDD_3V3", x: 30, y: -17.5 },
{ name: "C48", value: "100nF", jlc: "C71629", net: "VDD_1V8", x: -7, y: -22 },
{ name: "C49", value: "10pF", jlc: "C32949", net: "OSC_25M_XI", x: -3, y: 13.2 },
{ name: "C50", value: "10pF", jlc: "C32949", net: "OSC_25M_XO", x: 3, y: 13.2 },
// CAP_VDDS outputs must not share the dense underside PTH escape field.
// Hand-place them just outside U1 so each gets a short, via-free top route.
{ name: "C51", value: "1uF", jlc: "C318541", net: "CAP_VDDS_GENERAL1", x: 5, y: -10.5 },
{ name: "C52", value: "1uF", jlc: "C318541", net: "CAP_VDDS_MMC0", x: 7, y: -10.5 },
{ name: "C53", value: "1uF", jlc: "C318541", net: "CAP_VDDS_GPMC", x: -8.9, y: 0, rotation: 90 },
{ name: "C54", value: "1uF", jlc: "C318541", net: "CAP_VDDS_MMC2", x: -8.9, y: 2, rotation: 90 },
{ name: "C55", value: "1uF", jlc: "C318541", net: "CAP_VDDS_MMC1", x: 6, y: 13.2 },
{ name: "C56", value: "3.3uF", jlc: "C695126", net: "SD_IO", x: 8.5, y: 13.2, side: "top" },
// PMIC pin-local input and output capacitors.
{ name: "C57", value: "4.7uF", jlc: "C23733", net: "PROTECTED_5V", x: -18, y: 6, side: "bottom" },
{ name: "C58", value: "4.7uF", jlc: "C23733", net: "PROTECTED_5V", x: -18, y: 9, side: "bottom" },
{ name: "C59", value: "4.7uF", jlc: "C23733", net: "PROTECTED_5V", x: -14, y: 9, side: "bottom" },
{ name: "C60", value: "4.7uF", jlc: "C23733", net: "PROTECTED_5V", x: -11, y: 9, side: "bottom" },
{ name: "C61", value: "2.2uF", jlc: "C77002", net: "VDDA_1V8", x: -18, y: 2, side: "bottom" },
{ name: "C62", value: "2.2uF", jlc: "C77002", net: "VDD_RTC_0V75", x: -21, y: 0, side: "bottom" },
{ name: "C63", value: "220pF", jlc: "C1603", net: "SD_LOADSW_CT", x: -1, y: 29, side: "bottom" },
{ name: "C64", value: "22pF", jlc: "C70464", net: "SOC_PORz", x: -5, y: -20, side: "bottom" },
{ name: "C65", value: "4.7nF", jlc: "C1538", net: "EFUSE_DVDT", x: -31, y: -5, side: "bottom" },
{ name: "C66", value: "100nF", jlc: "C71629", net: "VDD_1V8", x: 5, y: 31, side: "bottom" },
// Raw-VBUS always-on CC detection and fail-safe enable logic.
{ name: "C67", value: "1uF", jlc: "C14445", net: "VBUS_RAW", x: -43, y: -2, side: "bottom" },
{ name: "C68", value: "1uF", jlc: "C14445", net: "AON_3V3", x: -41, y: -8, side: "bottom" },
{ name: "C69", value: "100nF", jlc: "C71629", net: "VBUS_RAW", x: -31, y: -7 },
{ name: "C70", value: "100nF", jlc: "C71629", net: "AON_3V3", x: -34.5, y: -14.5, side: "bottom" },
{ name: "C71", value: "100nF", jlc: "C71629", net: "AON_3V3", x: -24, y: -16, side: "bottom" },
{ name: "C72", value: "100nF", jlc: "C71629", net: "AON_3V3", x: -19, y: -10, side: "bottom" },
]
const supportResistors: ResistorSpec[] = [
{ name: "R3", value: "1k", jlc: "C11702", from: "POWER_LED_K", to: "GND", x: -34, y: -27 },
{ name: "R4", value: "10k", jlc: "C25744", from: "RESETz", to: "VDD_1V8", x: -2, y: -24 },
// Hand-aligned under the socket's non-numeric contact order: DAT2, DAT3,
// CMD, DAT0, DAT1. This prevents the five short pull-up branches crossing.
{ name: "R5", value: "47k", jlc: "C25792", from: "SD_CMD", to: "SD_IO", x: -15.575, y: 18.5, rotation: 90 },
{ name: "R6", value: "47k", jlc: "C25792", from: "SD_DAT0", to: "SD_IO", x: -11.175, y: 18.5, rotation: 90 },
{ name: "R7", value: "47k", jlc: "C25792", from: "SD_DAT1", to: "SD_IO", x: -10.075, y: 15.7, rotation: 90 },
{ name: "R8", value: "47k", jlc: "C25792", from: "SD_DAT2", to: "SD_IO", x: -17.775, y: 18.5, rotation: 90 },
{ name: "R9", value: "47k", jlc: "C25792", from: "SD_DAT3", to: "SD_IO", x: -16.675, y: 15.7, rotation: 90 },
{ name: "R10", value: "10k", jlc: "C25744", from: "SD_CARD_DETECT", to: "VDD_1V8", x: 1.5, y: 19 },
{ name: "R11", value: "100k", jlc: "C25741", from: "SD_PWR_EN", to: "GND", x: 4, y: 19 },
{ name: "R12", value: "10k", jlc: "C25744", from: "DDR0_RESET0_n", to: "GND", x: 43.25, y: 5 },
{ name: "R13", value: "2.2k", jlc: "C25879", from: "LPDDR4_ODT_CA", to: "VDD_DDR_1V1", x: 43.25, y: 2 },
{ name: "R14", value: "240", jlc: "C25094", from: "LPDDR4_ZQ", to: "GND", x: 43.25, y: -1 },
{ name: "R15", value: "240", jlc: "C25094", from: "DDR0_CAL0", to: "GND", x: 9.5, y: -10.5 },
// USB eFuse enable is fail-safe low; TUSB320 detection must actively drive it high.
{ name: "R16", value: "100k", jlc: "C25741", from: "EFUSE_EN", to: "GND", x: -31, y: -3, side: "bottom" },
{ name: "R17", value: "0", jlc: "C17168", from: "EFUSE_OVLO", to: "GND", x: -34, y: -3 },
{ name: "R18", value: "2.49k", jlc: "C25884", from: "EFUSE_ILM", to: "GND", x: -28, y: -3 },
// PMIC open-drain buses/status and 3V3 sequencing.
{ name: "R19", value: "4.7k", jlc: "C25900", from: "PMIC_I2C_SDA", to: "VDD_1V8", x: -21, y: 8 },
{ name: "R20", value: "4.7k", jlc: "C25900", from: "PMIC_I2C_SCL", to: "VDD_1V8", x: -21, y: 10 },
{ name: "R21", value: "10k", jlc: "C25744", from: "PMIC_nRSTOUT", to: "VDD_1V8", x: -21, y: 12 },
{ name: "R22", value: "10k", jlc: "C25744", from: "RTC_PORz", to: "VDD_1V8", x: -21, y: 14 },
{ name: "R23", value: "10k", jlc: "C25744", from: "PMIC_nINT", to: "VDD_1V8", x: -21, y: 16 },
{ name: "R24", value: "100k", jlc: "C25741", from: "EXT_3V3_EN", to: "VDD_1V8", x: -13, y: -2.8, side: "top" },
// TPS62A02 3.3V feedback and open-drain PG pull-up.
{ name: "R25", value: "453k", jlc: "C27009", from: "VDD_3V3", to: "EXT_3V3_FB", x: -14.8, y: -4.5, side: "top" },
{ name: "R26", value: "100k", jlc: "C25741", from: "EXT_3V3_FB", to: "GND", x: -12.2, y: -4.5, side: "top" },
{ name: "R27", value: "10k", jlc: "C25744", from: "EXT_3V3_PG", to: "VDD_1V8", x: -9.5, y: -4.76, side: "top" },
// SD default-on/reset gating and protected clock/card-detect paths.
{ name: "R28", value: "10k", jlc: "C25744", from: "SD_PWR_GPIO", to: "VDD_1V8", x: 6, y: 34 },
// TI recommends placing the MMC clock source-termination option at the SoC.
{ name: "R29", value: "0", jlc: "C17168", from: "SD_CLK_SOC", to: "SD_CLK", x: 11.25, y: 13.2, side: "top" },
{ name: "R30", value: "10k", jlc: "C25744", from: "SD_CLK", to: "GND", x: -2, y: 16 },
{ name: "R31", value: "100", jlc: "C25076", from: "SD_CARD_DETECT", to: "SD_CD_SOC", x: 3.8, y: 16 },
// Reduced BOOTMODE[15:12] = 1010 and unused wake input bias.
{ name: "R32", value: "10k", jlc: "C25744", from: "BOOTMODE15", to: "VDD_1V8", x: 10, y: 15.8, side: "bottom" },
{ name: "R33", value: "10k", jlc: "C25744", from: "BOOTMODE14", to: "GND", x: 12.5, y: 15.8, side: "bottom" },
{ name: "R34", value: "10k", jlc: "C25744", from: "BOOTMODE13", to: "VDD_1V8", x: 15, y: 12.5, side: "bottom" },
{ name: "R35", value: "10k", jlc: "C25744", from: "BOOTMODE12", to: "GND", x: 17.5, y: 12.5, side: "bottom" },
{ name: "R36", value: "10k", jlc: "C25744", from: "EXT_WAKEUP0_UNUSED", to: "GND", x: 20, y: 12.5, side: "bottom" },
{ name: "R37", value: "10k", jlc: "C25744", from: "EXT_WAKEUP1_UNUSED", to: "GND", x: 22.5, y: 12.5, side: "bottom" },
{ name: "R38", value: "47k", jlc: "C25792", from: "UART0_TX_1V8", to: "VDD_1V8", x: 19, y: -20 },
{ name: "R39", value: "47k", jlc: "C25792", from: "UART0_RX_1V8", to: "VDD_1V8", x: 23, y: -21.5 },
// TUSB320 GPIO pull-ups, VBUS_DET input resistor, and weak-supply LED current limit.
{ name: "R40", value: "4.7k", jlc: "C25900", from: "TUSB_OUT1", to: "AON_3V3", x: -36.5, y: -1, side: "bottom" },
{ name: "R41", value: "4.7k", jlc: "C25900", from: "TUSB_OUT2", to: "AON_3V3", x: -33.5, y: -1, side: "bottom" },
{ name: "R42", value: "909k", jlc: "C25799", from: "VBUS_RAW", to: "TUSB_VBUS_DET", x: -34, y: -7, side: "top" },
{ name: "R43", value: "1k", jlc: "C11702", from: "WEAK_USB_LED_K", to: "GND", x: -37.5, y: -12.5 },
]
const capacitorParts: Record<string, any> = {
C71629: GRM155R71C104KA88D,
C14445: CL05A105KP5NNNC,
C318541: CL03A105KQ3CSNC,
C18164586: TCC0201X7R104K160ZT,
C19702: CL10A106KP8NNNC,
C86295: CL10A226MP8NUNE,
C77002: GRM155R61A225KE95D,
C32949: CL05C100JB5NNNC,
C695126: C1005X5R1A335KTJ00E,
C23733: CL05A475MP5NRNC,
C1603: CL10B221KB8NNNC,
C70464: CL05C220JB5NNNC,
C1538: A_0402B472K500NT,
}
const resistorParts: Record<string, any> = {
C25905: A_0402WGF5101TCE,
C11702: A_0402WGF1001TCE,
C25744: A_0402WGF1002TCE,
C25741: A_0402WGF1003TCE,
C25094: A_0402WGF2400TCE,
C25879: A_0402WGF2201TCE,
C25792: A_0402WGF4702TCE,
C25900: A_0402WGF4701TCE,
C17168: A_0402WGF0000TCE,
C25076: A_0402WGF1000TCE,
C27009: A_0402WGF4533TCE,
C45194: A_0402WGF6651TCE,
C25884: A_0402WGF2491TCE,
C25799: A_0402WGF9093TCE,
}
const ROUTING_PHASE = {
ddr: 1,
sd: 2,
control: 3,
usbPower: 4,
powerAndGround: 5,
final: 6,
} as const
const getRoutingPhase = (from: string, to: string): number => {
const connection = `${from} ${to}`.toUpperCase()
if (/DDR0_(DQ\d+|DM\d+|DQS\d|DQS\d_N|A[0-5]\b|CS0_N|CKE0|CK0|CK0_N)/.test(connection)) {
return ROUTING_PHASE.ddr
}
if (/SD_PWR/.test(connection)) return ROUTING_PHASE.control
if (/SD_3V3|SD_IO|SD_LOADSW|CAP_VDDS_MMC1/.test(connection)) {
return ROUTING_PHASE.powerAndGround
}
if (/SD_|MMC1/.test(connection)) return ROUTING_PHASE.sd
if (/USB_|VBUS|TUSB|EFUSE|PROTECTED_5V|AON_3V3/.test(connection)) {
return ROUTING_PHASE.usbPower
}
if (/GND|VSS|VDD|VDDA|CAP_|3V3|1V8|0V75|_SW|_LX/.test(connection)) {
return ROUTING_PHASE.powerAndGround
}
return ROUTING_PHASE.control
}
const explicitRoutingNets = Array.from(
new Set([
...logicalTraces.flatMap(([from, to]) => [from, to]),
...socGroundTraces.flatMap(([from, to]) => [from, to]),
...socRailTraces.flatMap(([from, to]) => [from, to]),
...decouplingCapacitors.map(({ net }) => `net.${net}`),
...supportResistors.flatMap(({ from, to }) => [`net.${from}`, `net.${to}`]),
]
.filter((selector) => selector.startsWith("net."))
.map((selector) => selector.slice(4))),
).sort()
const ddrByte0Connections = [
...Array.from({ length: 8 }, (_, bit) => `DDR0_DQ${bit}`),
"DDR0_DM0",
"DDR0_DQS0",
"DDR0_DQS0_n",
]
const ddrByte1Connections = [
...Array.from({ length: 8 }, (_, bit) => `DDR0_DQ${bit + 8}`),
"DDR0_DM1",
"DDR0_DQS1",
"DDR0_DQS1_n",
]
const ddrCommandConnections = [
...Array.from({ length: 6 }, (_, bit) => `DDR0_A${bit}`),
"DDR0_CS0_n",
"DDR0_CKE0",
"DDR0_CK0",
"DDR0_CK0_n",
"DDR_LINK_RESET0_n",
]
const ddrFanoutLayers = ["inner2", "inner5", "bottom"] as const
const fixedTargetBgaBreakoutAutorouter = {
local: true,
groupMode: "subcircuit" as const,
algorithmFn: createFixedTargetBgaFanoutAutorouter,
}
const classifiedAutorouter = (phase: Parameters<typeof createAm62lClassifiedAutorouter>[0]["phase"], effort = 2) => ({
local: true,
groupMode: "subcircuit" as const,
algorithmFn: createAm62lClassifiedAutorouter({ phase, effort }),
})
export default () => (
<board
width="90mm"
height="75mm"
layers={8}
defaultTraceWidth="0.08128mm"
minTraceWidth="0.08128mm"
minTraceToPadEdgeClearance="0.08128mm"
minViaEdgeToPadEdgeClearance="0.08128mm"
minViaHoleEdgeToViaHoleEdgeClearance="0.1016mm"
minViaHoleDiameter="0.2032mm"
minViaPadDiameter="0.4572mm"
minPadEdgeToPadEdgeClearance="0mm"
pcbStyle={{ viaHoleDiameter: "0.2032mm", viaPadDiameter: "0.4572mm" }}
>
{explicitRoutingNets.map((name) => (
<Fragment key={name}>
<net name={name} routingPhaseIndex={getRoutingPhase(`net.${name}`, "")} />
</Fragment>
))}
<autoroutingphase
name="ddr-critical"
phaseIndex={ROUTING_PHASE.ddr}
autorouter="default"
/>
<autoroutingphase
name="microsd"
phaseIndex={ROUTING_PHASE.sd}
autorouter={classifiedAutorouter("sd", 3)}
/>
<autoroutingphase
name="clock-reset-control"
phaseIndex={ROUTING_PHASE.control}
autorouter={classifiedAutorouter("reset-control", 5)}
/>
<autoroutingphase
name="usb-power-entry"
phaseIndex={ROUTING_PHASE.usbPower}
autorouter={classifiedAutorouter("usb-power", 1)}
/>
<autoroutingphase
name="power-ground-local"
phaseIndex={ROUTING_PHASE.powerAndGround}
autorouter={classifiedAutorouter("power", 3)}
/>
<copperpour
name="GND_PLANE_L2"
layer="inner1"
connectsTo="net.GND"
unbroken
/>
<copperpour
name="GND_PLANE_L7"
layer="inner6"
connectsTo="net.GND"
unbroken
/>
<bus
name="DDR_BYTE0"
connections={ddrByte0Connections}
routingPhaseIndex={ROUTING_PHASE.ddr}
maxLengthSkew="0.25mm"
pcbTraceWidth="0.08128mm"
pcbAllowedLayers={["inner2"]}
preferredLayer="inner2"
/>
<bus
name="DDR_BYTE1"
connections={ddrByte1Connections}
routingPhaseIndex={ROUTING_PHASE.ddr}
maxLengthSkew="0.25mm"
pcbTraceWidth="0.08128mm"
pcbAllowedLayers={["bottom"]}
preferredLayer="bottom"
/>
<bus
name="DDR_COMMAND"
connections={ddrCommandConnections}
routingPhaseIndex={ROUTING_PHASE.ddr}
maxLengthSkew="0.5mm"
pcbTraceWidth="0.09398mm"
pcbAllowedLayers={["inner5"]}
preferredLayer="inner5"
/>
<breakout
name="SOC_BREAKOUT"
pcbX={2}
pcbY={1}
padding="5mm"
autorouter={fixedTargetBgaBreakoutAutorouter}
fanoutBoundaryPadding={{
top: "5mm",
right: "2mm",
bottom: "5mm",
left: "1mm",
}}
fanoutRoutingLayers={[...ddrFanoutLayers]}
busFanoutDirections={{
DDR_BYTE1: "top_right",
DDR_COMMAND: "center_right",
DDR_BYTE0: "bottom_right",
}}
>
<AM62L32 name="U1" footprintVariant="fccsp_373_anb" pcbX={0} pcbY={0}
pcbRotation={180} noSchematicRepresentation
{...pinMetadata(373, socConnected, socAttributes)} />
</breakout>
<breakout
name="RAM_BREAKOUT"
pcbX={29.675}
pcbY={1 + TI_AM62L_EVM_MEMORY_OFFSET.y}
padding="5mm"
autorouter={fixedTargetBgaBreakoutAutorouter}
fanoutBoundaryPadding={{
top: "5mm",
right: "1mm",
bottom: "5mm",
left: "2mm",
}}
fanoutRoutingLayers={[...ddrFanoutLayers]}
busFanoutDirections={{
DDR_BYTE1: "top_left",
DDR_COMMAND: "center_left",
DDR_BYTE0: "bottom_left",
}}
>
<RegistryMt53e1g16 name="U2"
pcbX={0}
pcbY={0}
pcbRotation={90}
noSchematicRepresentation />
</breakout>
<TPS6521401VAFR
name="U3"
pcbX={-15}
pcbY={4}
noSchematicRepresentation
noConnect={pinMetadata(24, Array.from({ length: 24 }, (_, index) => index + 1)).noConnect}
/>
<USB4125_GF_A_0190 name="U12" pcbX={-42} pcbY={0} pcbRotation={-90} noSchematicRepresentation
{...pinMetadata(16, [7, 8, 9, 10, 11, 12, 13, 14, 15, 16], {
7: { requiresGround: true }, 8: { requiresGround: true }, 9: { requiresGround: true }, 10: { requiresGround: true },
11: { requiresGround: true }, 12: { requiresPower: true, providesPower: true },
15: { requiresPower: true, providesPower: true }, 16: { requiresGround: true },
})} />
<TPS259470LRPWR name="U4" pcbX={-31} pcbY={0} noSchematicRepresentation {...pinMetadata(10, [1, 2, 5, 6, 7, 8, 9], { 5: { requiresPower: true }, 6: { providesPower: true }, 8: { requiresGround: true } })} />
<TUSB320LAIRWBR name="U21" pcbX={-37} pcbY={-5} noSchematicRepresentation
{...pinMetadata(12, [1, 2, 3, 4, 7, 8, 10, 11, 12], {
10: { requiresGround: true }, 12: { requiresPower: true },
})} />
<TLV75533PDBVR name="U22" pcbX={-40} pcbY={-5} layer="bottom" noSchematicRepresentation
{...pinMetadata(5, [1, 2, 3, 5], {
1: { requiresPower: true }, 2: { requiresGround: true }, 5: { providesPower: true },
})} />
<SN74LVC1G04DBVR name="U23" pcbX={-35} pcbY={-9} layer="bottom" noSchematicRepresentation
{...pinMetadata(5, [2, 3, 4, 5], { 3: { requiresGround: true }, 5: { requiresPower: true } })} />
<SN74LVC1G04DBVR name="U24" pcbX={-29} pcbY={-13} layer="bottom" noSchematicRepresentation
{...pinMetadata(5, [2, 3, 4, 5], { 3: { requiresGround: true }, 5: { requiresPower: true } })} />
<SN74LVC1G08DBVR name="U25" pcbX={-24} pcbY={-10} layer="bottom" noSchematicRepresentation
{...pinMetadata(5, [1, 2, 3, 4, 5], { 3: { requiresGround: true }, 5: { requiresPower: true } })} />
<TPS62A02DRLR name="U5" pcbX={-14} pcbY={-7} noSchematicRepresentation {...pinMetadata(6, [1, 2, 3, 4, 5, 6], { 1: { requiresGround: true }, 2: { providesPower: true }, 3: { requiresPower: true } })} />
<DFE201612PD_1R0M_P2 name="L1" pcbX={-10.4} pcbY={-7} />
<XRCGB25M000F3A00R0 name="Y1" pcbX={0} pcbY={13.2} />
<DM3AT_SF_PEJM5 name="U15" pcbX={-15} pcbY={29} pcbRotation={180} noSchematicRepresentation {...pinMetadata(14, [1, 2, 3, 4, 5, 6, 7, 8, 9, 11], { 4: { requiresPower: true }, 6: { requiresGround: true } })} />
<TPS22918DBVR name="U6" pcbX={-2} pcbY={27} noSchematicRepresentation {...pinMetadata(6, [1, 2, 3, 4, 6], { 1: { requiresPower: true }, 2: { requiresGround: true }, 6: { providesPower: true } })} />
<TPD4E02B04DQAR name="U7" pcbX={-5} pcbY={23} noSchematicRepresentation {...pinMetadata(10, [1, 2, 3, 4, 5, 8], { 1: { requiresPower: true }, 3: { requiresGround: true }, 8: { requiresGround: true } })} />
<TPD4E02B04DQAR name="U8" pcbX={1} pcbY={16} noSchematicRepresentation {...pinMetadata(10, [1, 2, 3, 4, 8], { 1: { requiresPower: true }, 3: { requiresGround: true }, 8: { requiresGround: true } })} />
<SN74AXC1T45DBVR name="U9" pcbX={22} pcbY={-17} noSchematicRepresentation {...pinMetadata(6, [1, 2, 3, 4, 5, 6], { 1: { requiresPower: true }, 2: { requiresGround: true }, 6: { requiresPower: true } })} />
<SN74AXC1T45DBVR name="U10" pcbX={27} pcbY={-21} noSchematicRepresentation {...pinMetadata(6, [1, 2, 3, 4, 5, 6], { 1: { requiresPower: true }, 2: { requiresGround: true }, 6: { requiresPower: true } })} />
<TPD2E2U06DCKR name="U16" pcbX={31.5} pcbY={-24} pcbRotation={90} noSchematicRepresentation {...pinMetadata(3, [1, 2, 3], { 1: { requiresPower: true }, 3: { requiresGround: true } })} />
<S4B_PH_SM4_K_TB_LF__SN_ name="U17" pcbX={40} pcbY={-20} pcbRotation={-90} noSchematicRepresentation {...pinMetadata(6, [1, 2, 3, 4], { 3: { requiresGround: true }, 4: { requiresPower: true } })} />
<SKRPACE010 name="SW1" pcbX={-2} pcbY={-28} schMarginY="2mm" noSchematicRepresentation {...pinMetadata(4, [1, 2, 3, 4])} />
<SN74LVC1G08DBVR name="U11" pcbX={-8} pcbY={-18} noSchematicRepresentation {...pinMetadata(5, [1, 2, 3, 4, 5], { 3: { requiresGround: true }, 5: { requiresPower: true } })} />
<SN74LVC1G08DBVR name="U20" pcbX={0} pcbY={32} layer="bottom" noSchematicRepresentation {...pinMetadata(5, [1, 2, 3, 4, 5], { 3: { requiresGround: true }, 5: { requiresPower: true } })} />
<SMF5_0A name="D2" pcbX={-38} pcbY={2.5} pcbRotation={90} />
<testpoint name="TP_BOOT15" footprintVariant="pad" padShape="circle" padDiameter="1mm" pcbX={15} pcbY={33} schX={50} schY={16} />
<testpoint name="TP_BOOT14" footprintVariant="pad" padShape="circle" padDiameter="1mm" pcbX={21} pcbY={33} schX={50} schY={12} />
<testpoint name="TP_BOOT13" footprintVariant="pad" padShape="circle" padDiameter="1mm" pcbX={27} pcbY={33} schX={50} schY={8} />
<testpoint name="TP_BOOT12" footprintVariant="pad" padShape="circle" padDiameter="1mm" pcbX={33} pcbY={33} schX={50} schY={4} />
<testpoint name="TP_CC1" footprintVariant="pad" padShape="circle" padDiameter="1mm" pcbX={-40} pcbY={-32} layer="bottom" schX={50} schY={0} />
<testpoint name="TP_CC2" footprintVariant="pad" padShape="circle" padDiameter="1mm" pcbX={-36} pcbY={-32} layer="bottom" schX={50} schY={-4} />
<testpoint name="TP_TUSB_OUT1" footprintVariant="pad" padShape="circle" padDiameter="1mm" pcbX={-32} pcbY={-32} layer="bottom" schX={50} schY={-8} />
<testpoint name="TP_EFUSE_EN" footprintVariant="pad" padShape="circle" padDiameter="1mm" pcbX={-28} pcbY={-32} layer="bottom" schX={50} schY={-12} />
<testpoint name="TP_PROTECTED_5V" footprintVariant="pad" padShape="circle" padDiameter="1mm" pcbX={-24} pcbY={-32} layer="bottom" schX={50} schY={-16} />
{/* TPS6521401 buck inductors from the original candidate BOM. */}
<TFM201208BLE_R47MTCF name="L2" pcbX={-11} pcbY={0} />
<TFM201208BLE_R47MTCF name="L3" pcbX={-11} pcbY={3.5} />
<TFM201208BLE_R47MTCF name="L4" pcbX={-11} pcbY={7} />
<trace name="PMIC_B1_LX" from="L2.pin1" to="net.PMIC_BUCK1_SW" routingPhaseIndex={ROUTING_PHASE.powerAndGround} />
<trace name="PMIC_B1_OUT" from="L2.pin2" to="net.VDD_CORE_0V75" routingPhaseIndex={ROUTING_PHASE.powerAndGround} />
<trace name="PMIC_B2_LX" from="L3.pin1" to="net.PMIC_BUCK2_SW" routingPhaseIndex={ROUTING_PHASE.powerAndGround} />
<trace name="PMIC_B2_OUT" from="L3.pin2" to="net.VDD_1V8" routingPhaseIndex={ROUTING_PHASE.powerAndGround} />
<trace name="PMIC_B3_LX" from="L4.pin1" to="net.PMIC_BUCK3_SW" routingPhaseIndex={ROUTING_PHASE.powerAndGround} />
<trace name="PMIC_B3_OUT" from="L4.pin2" to="net.VDD_DDR_1V1" routingPhaseIndex={ROUTING_PHASE.powerAndGround} />
{decouplingCapacitors.map(({ name, jlc, net, x, y, rotation, side }) => {
const Part = capacitorParts[jlc]
return <Fragment key={name}>
<Part name={name} pcbX={x} pcbY={y} pcbRotation={rotation} layer={side} />
<trace name={`${name}_${net}`} from={`${name}.pin1`} to={`net.${net}`}
routingPhaseIndex={ROUTING_PHASE.powerAndGround} />
<trace name={`${name}_GND`} from={`${name}.pin2`} to="net.GND"
routingPhaseIndex={ROUTING_PHASE.powerAndGround} />
</Fragment>
})}
<LTST_C190KGKT name="D1" pcbX={-38} pcbY={-27} {...pinMetadata(2, [1, 2])} />
<LTST_C190KRKT name="D3" pcbX={-40} pcbY={-8} {...pinMetadata(2, [1, 2])} />
{supportResistors.map(({ name, jlc, from, to, x, y, rotation, side }) => {
const Part = resistorParts[jlc]
return <Fragment key={name}>
<Part name={name} pcbX={x} pcbY={y} pcbRotation={rotation} layer={side} />
<trace name={`${name}_${from}`} from={`${name}.pin1`} to={`net.${from}`}
routingPhaseIndex={getRoutingPhase(`${name}.pin1`, `net.${from}`)} />
<trace name={`${name}_${to}`} from={`${name}.pin2`} to={`net.${to}`}
routingPhaseIndex={getRoutingPhase(`${name}.pin2`, `net.${to}`)} />
</Fragment>
})}
{[...logicalTraces, ...socGroundTraces, ...socRailTraces].map(([from, to], index) => (
<Fragment key={`${from}-${to}-${index}`}>
<trace name={`N${index + 1}`} from={from} to={to}
routingPhaseIndex={getRoutingPhase(from, to)} />
</Fragment>
))}
<trace name="U1_R9_DIRECT_VDD_CORE_0V75" from="U1.pin229" to="net.VDD_CORE_0V75"
routingPhaseIndex={ROUTING_PHASE.powerAndGround} />
{ddrSignals.map(([soc, memory]) => (
<Fragment key={soc}>
<trace name={soc === "DDR0_RESET0_n" ? "DDR_LINK_RESET0_n" : soc} from={`U1.${soc}`} to={`U2.${memory}`}
routingPhaseIndex={ROUTING_PHASE.ddr} />
</Fragment>
))}
<silkscreentext text="J1 5V POWER ONLY" pcbX={-39} pcbY={6} fontSize={0.7} />
<silkscreentext text="J2 microSD" pcbX={-31} pcbY={35} fontSize={0.7} />
<silkscreentext text="J3 UART 3V3" pcbX={38} pcbY={-27} fontSize={0.7} />
<silkscreentext text="WEAK USB SUPPLY" pcbX={-39} pcbY={-11} fontSize={0.55} />
<silkscreentext text="SIMPLIFIED AM62L COMPUTER - 8 LAYER 90x75 - LOGICAL NETLIST DRAFT" pcbX={0} pcbY={-34} fontSize={0.7} />
</board>
)
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