0hmX/simplified-am62l-computer

This code defines components and scripts for physically representing and routing high-speed DDR memory signals, power lines, and ground planes on an 8-layer PCB with detailed pin assignments, copper pours, and precise via and trace layouts based on TI EVM reference data.

Version
1.0.16
License
unset
Stars
0

ddr-only-connections.ts

/** Direct AM62L-to-MT53E1G16 LPDDR4 connections from the TI TMDS62LEVM. */
export const DDR_ONLY_CONNECTIONS = [
  ...Array.from(
    { length: 16 },
    (_, bit) => [`DDR0_DQ${bit}`, `DQ${bit}`] as const,
  ),
  ["DDR0_DM0", "DMI0"],
  ["DDR0_DM1", "DMI1"],
  ["DDR0_DQS0", "DQS0_t"],
  ["DDR0_DQS0_n", "DQS0_c"],
  ["DDR0_DQS1", "DQS1_t"],
  ["DDR0_DQS1_n", "DQS1_c"],
  ["DDR0_A0", "CA0"],
  ["DDR0_A1", "CA1"],
  ["DDR0_A2", "CA2"],
  ["DDR0_A3", "CA3"],
  ["DDR0_A4", "CA4"],
  ["DDR0_A5", "CA5"],
  ["DDR0_CS0_n", "CS"],
  ["DDR0_CKE0", "CKE"],
  ["DDR0_CK0", "CK_t"],
  ["DDR0_CK0_n", "CK_c"],
  ["DDR0_RESET0_n", "RESET_n"],
] as const

// Physical AM62L package pins used by the 33 direct connections above.
export const DDR_ONLY_SOC_PINS = [
  76, 91, 92, 93, 94, 103, 104, 105, 121, 122, 123, 124, 125, 139,
  140, 149, 150, 162, 164, 165, 215, 216, 236, 238, 255, 256, 257,
  272, 273, 275, 276, 284, 285,
] as const