MustafaMulla29/ti-chip
This code models a hardware circuit for a motor driver using a DRV83053QPHPQ1 integrated circuit, with power supply bypass capacitors, charge-pump capacitors, resistors, and filters, representing the physical connections and key components in a motor control power stage.
- Version
- 0.0.1
- License
- unset
- Stars
- 0
index.tsx
PCB
Schematic
import "tscircuit";
import { DRV83053QPHPQ1 } from "./DRV83053QPHPQ1";
/**
* DRV8305-Q1 reference subcircuit extracted from TIDA-01330 sheet 2.
*
* Scope: U1 and the passives wired directly around U1. The external
* SQJ858AEP inverter stages are exposed as named nets because they are a
* separate power stage in the complete reference design.
*/
export const MotorDriver_DRV8305_TIDA01330 = () => (
<board
title="TIDA-01330 DRV8305-Q1 reference subcircuit"
routingDisabled
schMaxTraceDistance="4mm"
>
<net name="GND" isGroundNet />
<net name="PVDD" isPowerNet />
<DRV83053QPHPQ1
name="U1"
schX={0}
schY={0}
schWidth={2.43}
schHeight={13.0}
schPinArrangement={{
leftSide: {
direction: "top-to-bottom",
pins: [
15, 46, 41, 8, 12, 10, 11, 9, 1, 2, 3, 4, 5, 6, 7, 16, 17, 18, 37,
38,
],
},
rightSide: {
direction: "top-to-bottom",
pins: [
43, 42, 39, 40, 47, 48, 13, 44, 36, 35, 33, 34, 29, 31, 32, 30, 28,
27, 25, 26, 23, 24, 21, 22, 19, 20, 14, 45, 49,
],
},
}}
schPinStyle={{
pin15: { marginBottom: 0.4 },
pin46: { marginBottom: 0.4 },
pin41: { marginBottom: 0.2 },
pin8: { marginBottom: 0.1 },
pin12: { marginBottom: 0.1 },
pin10: { marginBottom: 0.1 },
pin11: { marginBottom: 0.1 },
pin9: { marginBottom: 0.1 },
pin1: { marginBottom: 0.4 },
pin2: { marginBottom: 0.4 },
pin3: { marginBottom: 0.8 },
pin4: { marginBottom: 0.4 },
pin5: { marginBottom: 0.8 },
pin6: { marginBottom: 0.4 },
pin7: { marginBottom: 1.8 },
pin16: { marginBottom: 0.4 },
pin17: { marginBottom: 0.4 },
pin18: { marginBottom: 0.6 },
pin37: { marginBottom: 0.4 },
pin43: { marginBottom: 0.4 },
pin42: { marginBottom: 0.4 },
pin39: { marginBottom: 0.25 },
pin40: { marginBottom: 0.1 },
pin47: { marginBottom: 0.1 },
pin48: { marginBottom: 0.1 },
pin13: { marginBottom: 0.1 },
pin44: { marginBottom: 0.7 },
pin36: { marginBottom: 0.4 },
pin35: { marginBottom: 0.1 },
pin33: { marginBottom: 0.1 },
pin34: { marginBottom: 0.2 },
pin29: { marginBottom: 0.4 },
pin31: { marginBottom: 0.1 },
pin32: { marginBottom: 0.1 },
pin30: { marginBottom: 0.2 },
pin28: { marginBottom: 0.4 },
pin27: { marginBottom: 0.2 },
pin25: { marginBottom: 0.2 },
pin26: { marginBottom: 0.3 },
pin23: { marginBottom: 0.2 },
pin24: { marginBottom: 0.3 },
pin21: { marginBottom: 0.2 },
pin22: { marginBottom: 0.3 },
pin19: { marginBottom: 0.2 },
pin20: { marginBottom: 0.3 },
pin14: { marginBottom: 0.1 },
pin45: { marginBottom: 0.1 },
}}
/>
{/* AVDD, DVDD and PVDD bypassing, placed as in the reference. */}
<capacitor
name="C14"
capacitance="1uF"
footprint="0402"
schX={-5.2}
schY={5.6}
schOrientation="vertical"
/>
<capacitor
name="C16"
capacitance="1uF"
footprint="0402"
schX={-4.1}
schY={5.0}
schOrientation="vertical"
/>
<capacitor
name="C17"
capacitance="4.7uF"
footprint="0402"
schX={-3.3}
schY={4.4}
schOrientation="vertical"
/>
<trace from=".U1 > .AVDD" to=".C14 > .pin1" />
<trace from=".U1 > .AVDD" to="net.AVDD" schDisplayLabel="AVDD" />
<trace from=".U1 > .DVDD" to=".C16 > .pin1" />
<trace from=".U1 > .DVDD" to="net.DVDD" schDisplayLabel="DVDD" />
<trace from=".U1 > .PVDD" to=".C17 > .pin1" />
<trace from=".U1 > .PVDD" to="net.PVDD" schDisplayLabel="PVDD" />
<trace from=".C14 > .pin2" to=".C16 > .pin2" />
<trace from=".C16 > .pin2" to=".C17 > .pin2" />
<trace from=".C14 > .pin2" to="net.GND" schDisplayLabel="GND" />
{/* Charge-pump flying capacitors. */}
<capacitor
name="C13"
capacitance="0.047uF"
footprint="0402"
schX={2.8}
schY={6.07}
schOrientation="horizontal"
/>
<capacitor
name="C15"
capacitance="0.047uF"
footprint="0402"
schX={2.8}
schY={4.87}
schOrientation="horizontal"
/>
<trace from=".U1 > .CP1H" to=".C13 > .pin1" />
<trace from=".U1 > .CP1L" to=".C13 > .pin2" />
<trace from=".U1 > .CP2H" to=".C15 > .pin1" />
<trace from=".U1 > .CP2L" to=".C15 > .pin2" />
{/* PWRGD/reset and VDRAIN networks. */}
<resistor
name="R7"
resistance="56ohm"
footprint="0402"
schX={3.5}
schY={3.4}
/>
<resistor
name="R8"
resistance="100ohm"
footprint="0402"
schX={3.0}
schY={2.6}
/>
<capacitor
name="C18"
capacitance="1uF"
footprint="0402"
schX={5.0}
schY={3}
schOrientation="vertical"
/>
{/* <schematicsymbol
name="V3V3_RESET"
displayName="3p3V"
symbolName="rail_up"
schX={5.0}
schY={4.2}
/> */}
<trace name="PWRGD" from=".U1 > .PWRGD" to=".R7 > .pin1" />
<trace from=".R7 > .pin2" to="net.nRESET" schDisplayLabel="nRESET" />
{/* <trace from=".R7 > .pin2" to=".C18 > .pin1" /> */}
<trace from=".C18 > .pin1" to="net.V3p3" />
<trace from=".U1 > .VREG" to=".C18 > .pin1" />
<trace from=".C18 > .pin2" to="net.GND" schDisplayLabel="GND" />
<trace from=".U1 > .VDRAIN" to=".R8 > .pin1" />
<trace from=".R8 > .pin2" to="net.PVDD" schDisplayLabel="PVDD" />
{/* Current-amplifier output filters. */}
<resistor
name="R14"
resistance="56ohm"
footprint="0402"
schX={-4}
schY={-3.4}
/>
<resistor
name="R15"
resistance="56ohm"
footprint="0402"
schX={-4}
schY={-4.1}
/>
<resistor
name="R16"
resistance="56ohm"
footprint="0402"
schX={-4}
schY={-4.8}
/>
<capacitor
name="C22"
capacitance="2200pF"
footprint="0402"
schX={-7}
schY={-6.2}
schOrientation="vertical"
/>
<capacitor
name="C23"
capacitance="2200pF"
footprint="0402"
schX={-6}
schY={-6.2}
schOrientation="vertical"
/>
<capacitor
name="C24"
capacitance="2200pF"
footprint="0402"
schX={-5.1}
schY={-6.2}
schOrientation="vertical"
/>
<trace from=".U1 > .SO1" to=".R14 > .pin2" />
<trace from=".U1 > .SO2" to=".R15 > .pin2" />
<trace from=".U1 > .SO3" to=".R16 > .pin2" />
<trace from=".R14 > .pin1" to="net.ISNS_A" schDisplayLabel="ISNS_A" />
<trace from=".R15 > .pin1" to="net.ISNS_B" schDisplayLabel="ISNS_B" />
<trace from=".R16 > .pin1" to="net.ISNS_C" schDisplayLabel="ISNS_C" />
<trace from=".R14 > .pin1" to=".C22 > .pin1" />
<trace from=".R15 > .pin1" to=".C23 > .pin1" />
<trace from=".R16 > .pin1" to=".C24 > .pin1" />
<trace from=".C22 > .pin2" to=".C23 > .pin2" />
<trace from=".C23 > .pin2" to=".C24 > .pin2" />
<trace from=".C24 > .pin2" to=".C26 > .pin2" />
{/* Low-side and main charge-pump reservoirs. */}
<capacitor
name="C26"
capacitance="1uF"
footprint="0402"
schX={-3.9}
schY={-6.3}
schOrientation="vertical"
/>
<capacitor
name="C27"
capacitance="2.2uF"
footprint="0402"
schX={-2.4}
schY={-6.05}
/>
<trace from=".U1 > .VCP_LSD" to=".C26 > .pin1" />
<trace from=".C26 > .pin2" to="net.GND" schDisplayLabel="GND" />
<trace name="VCPH" from=".U1 > .VCPH" to=".C27 > .pin2" />
<trace from=".C27 > .pin1" to="net.PVDD" schDisplayLabel="PVDD" />
{/* Differential shunt-input filters. */}
<capacitor
name="C20"
capacitance="1000pF"
footprint="0402"
schX={3.5}
schY={-2.5}
schOrientation="vertical"
/>
<capacitor
name="C21"
capacitance="1000pF"
footprint="0402"
schX={3.5}
schY={-3.8}
schOrientation="vertical"
/>
<capacitor
name="C25"
capacitance="1000pF"
footprint="0402"
schX={3.5}
schY={-5.2}
schOrientation="vertical"
/>
<trace from=".U1 > .SN1" to=".C20 > .pin1" />
<trace from=".U1 > .SP1" to=".C20 > .pin2" />
<trace from=".U1 > .SN2" to=".C21 > .pin1" />
<trace from=".U1 > .SP2" to=".C21 > .pin2" />
<trace from=".U1 > .SN3" to=".C25 > .pin1" />
<trace from=".U1 > .SP3" to=".C25 > .pin2" />
<trace from=".C20 > .pin1" to="net.S1_N" />
<trace from=".C20 > .pin2" to="net.S1_P" />
<trace from=".C21 > .pin1" to="net.S2_N" />
<trace from=".C21 > .pin2" to="net.S2_P" />
<trace from=".C25 > .pin1" to="net.S3_N" />
<trace from=".C25 > .pin2" to="net.S3_P" />
{/* U1 ground pins. */}
<trace from=".U1 > .GND3" to=".U1 > .GND2" />
<trace from=".U1 > .GND2" to=".U1 > .GND1" />
<trace from=".U1 > .GND1" to="net.GND" schDisplayLabel="GND" />
{/* Left-side control and current-sense boundary nets. */}
<trace from=".U1 > .nFAULT" to="net.nFAULT" />
<trace from=".U1 > .SCLK" to="net.TILT_P" schDisplayLabel="TILT+" />
<trace from=".U1 > .SDI" to="net.BACK" />
<trace from=".U1 > .SDO" to="net.FWD" />
<trace from=".U1 > .nSCS" to="net.nSCS" schDisplayLabel="nCS" />
<trace from=".U1 > .EN_GATE" to="net.EN_GATE" />
<trace from=".U1 > .INHA" to="net.AH" />
<trace from=".U1 > .INLA" to="net.AL" />
<trace from=".U1 > .INHB" to="net.BH" />
<trace from=".U1 > .INLB" to="net.BL" />
<trace from=".U1 > .INHC" to="net.CH" />
<trace from=".U1 > .INLC" to="net.CL" />
{/* Gate-driver outputs terminate at the U1 subcircuit boundary. */}
<trace from=".U1 > .WAKE" to="net.WAKE" />
<trace from=".U1 > .GHA" to="net.GH_A" />
<trace from=".U1 > .SHA" to="net.MOT_A" />
<trace from=".U1 > .GLA" to="net.GL_A" />
<trace from=".U1 > .SLA" to="net.SL_A" />
<trace from=".U1 > .GHB" to="net.GH_B" />
<trace from=".U1 > .SLB" to="net.SL_B" />
<trace from=".U1 > .GLB" to="net.GL_B" />
<trace from=".U1 > .SHB" to="net.MOT_B" />
<trace from=".U1 > .GHC" to="net.GH_C" />
<trace from=".U1 > .SHC" to="net.MOT_C" />
<trace from=".U1 > .GLC" to="net.GL_C" />
<trace from=".U1 > .SLC" to="net.SL_C" />
</board>
);
export default MotorDriver_DRV8305_TIDA01330;