0hmX/am62l-lpddr4-breakout-repro
This code defines the physical layout, pin assignments, and power connections for the TI AM62L system-on-chip with DDR4/LPDDR4 memory, including detailed component placement, decoupling capacitors, and signal traces for a 6-layer PCB design.
- Version
- 1.0.14
- License
- unset
- Stars
- 0
pcbpack-fixed-bga-bottom-decoupling-repro.circuit.tsx
import { Fragment } from "react"
type ReproProps = {
fixedBga?: boolean
capacitorCount?: number
boardWidth?: string
boardHeight?: string
}
const bgaPinPairs = [
[15, 16],
[21, 22],
[9, 10],
[27, 28],
[3, 4],
[33, 34],
[13, 14],
[19, 20],
[7, 8],
[25, 26],
[1, 2],
[31, 32],
] as const
/**
* Minimal control/repro for layer-aware pcbPack behavior.
*
* Default: the top BGA is fixed at the origin, matching the AM62L floorplan.
* Control: inject { "fixedBga": false } to match Core's passing reference test.
*/
export default ({
fixedBga = true,
capacitorCount = 2,
boardWidth = "16mm",
boardHeight = "14mm",
}: ReproProps = {}) => {
if (capacitorCount < 1 || capacitorCount > bgaPinPairs.length) {
throw new Error(`capacitorCount must be between 1 and ${bgaPinPairs.length}`)
}
const bgaPosition = fixedBga ? { pcbX: 0, pcbY: 0 } : {}
return (
<board
width={boardWidth}
height={boardHeight}
pcbPack
pcbGap="0.2mm"
routingDisabled
>
<chip
name="U1"
footprint="bga36_grid6x6_p0.8mm_pad0.35mm_circularpads"
{...bgaPosition}
/>
{bgaPinPairs.slice(0, capacitorCount).map(([powerPin, groundPin], index) => {
const name = `C${index + 1}`
return (
<Fragment key={name}>
<capacitor
name={name}
capacitance="100nF"
footprint="0402"
layer="bottom"
/>
<trace from={`U1.pin${powerPin}`} to={`${name}.pin1`} />
<trace from={`U1.pin${groundPin}`} to={`${name}.pin2`} />
</Fragment>
)
})}
</board>
)
}