0hmX/am62l-lpddr4-breakout-repro

This code defines the physical layout, pin assignments, and power connections for the TI AM62L system-on-chip with DDR4/LPDDR4 memory, including detailed component placement, decoupling capacitors, and signal traces for a 6-layer PCB design.

Version: 1.0.14
License: unset
Stars: 0

RESULTS.md

# Routing results

## Before — registry release 1.0.7

- `tscircuit`: `0.0.2332`
- `@tscircuit/core`: `0.0.1685`
- Byte-1 buses had no `preferredLayer` assignments.
- The focused fanouts completed, but DQ9 and DQ10 exited on `inner2` at the SoC
  and `bottom` at the RAM.
- The published 1.0.7 registry build failed and did not produce a current PCB
  preview.

## After — 2026-08-19

- `tscircuit`: `0.0.2356`
- `@tscircuit/core`: `0.0.1703`
- Core npm `gitHead`: `23817c9f55dc36a1b647b52dd27152ee51e55ba5`
- Both breakout paddings: 2 mm
- Autorouter effort: `1x` (the previous `10x` setting exceeded the registry's
  300-second per-file build limit)
- Byte-1 shared bus preferences:
  - DQ9, DQ10: `inner2`
  - DQ11, DQ12, DQ14: `bottom`
  - DQ8, DQ13, DQS1, DQS1_n: `inner3`
  - DQ15, DM1: `inner2`

The same bus declarations are consumed by both breakout autorouting phases, so
each preference applies to the SoC and RAM ends together.

## Verification

- TypeScript: passed
- Netlist: 0 errors, 0 warnings
- Schematic placement: passed
- PCB placement: 0 errors, 0 warnings
- SoC fanout: 11/11 traces, 0 errors
- RAM fanout: 11/11 traces, 0 errors
- Global route: 11/11 traces, 0 autorouter errors
- Cloud-equivalent focused build: passed in 39.3 seconds
- Layer comparison: 11/11 SoC/RAM pairs matched
- Copper shorts: none detected

The complete route currently reports one clearance diagnostic between DQS1_n
and DQ13: 0.038 mm measured gap. This reproduction still omits the electrical
and manufacturing constraints listed in the README and is not a production DDR
layout.